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CAT28LV65KI-35T

Description
64K-Bit CMOS PARALLEL E2PROM
Categorystorage    storage   
File Size57KB,10 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT28LV65KI-35T Overview

64K-Bit CMOS PARALLEL E2PROM

CAT28LV65KI-35T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCatalyst
Parts packaging codeSOIC
package instructionSOP,
Contacts28
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time350 ns
Other features100000 PROGRAM/ERASE CYCLES; 100 YEAR DATA RETENTION
Data retention time - minimum100
JESD-30 codeR-PDSO-G28
JESD-609 codee0
length17.9 mm
memory density65536 bi
Memory IC TypeEEPROM
memory width8
Humidity sensitivity level1
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Programming voltage3 V
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
Preliminary
CAT28LV65
64K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
3.0V to 3.6V Supply
s
Read Access Times:
s
CMOS and TTL Compatible I/O
s
Automatic Page Write Operation:
– 250/300/350ns
s
Low Power CMOS Dissipation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s
End of Write Detection:
– Active: 8 mA Max.
– Standby: 100
µ
A Max.
s
Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
– Toggle Bit
DATA
Polling
– RDY/BUSY
BUSY
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
– 5ms Max.
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV65 is a low voltage, low power, CMOS
parallel E
2
PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling, RDY/BUSY and Toggle status bit signal
the start and end of the self-timed write cycle. Addition-
ally, the CAT28LV65 features hardware and software
write protection.
The CAT28LV65 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING,
RDY/BUSY &
TOGGLE BIT
COLUMN
DECODER
28LV65 F01
I/O0–I/O7
A0–A4
RDY/BUSY
ADDR. BUFFER
& LATCHES
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25041-00 2/98
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