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CAT28F102N-45T

Description
1 Megabit CMOS Flash Memory
Categorystorage    storage   
File Size125KB,14 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT28F102N-45T Overview

1 Megabit CMOS Flash Memory

CAT28F102N-45T Parametric

Parameter NameAttribute value
MakerCatalyst
Parts packaging codeLCC
package instructionQCCJ,
Contacts44
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time45 ns
Other features10 YEAR DATA RETENTION; 100000 PROGRAM/ERASE CYCLES
Data retention time - minimum10
JESD-30 codeS-PQCC-J44
length16.5862 mm
memory density1048576 bi
Memory IC TypeFLASH
memory width16
Number of functions1
Number of terminals44
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX16
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Programming voltage12 V
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
typeNOR TYPE
width16.5862 mm
CAT28F102
1 Megabit CMOS Flash Memory
FEATURES
s
Fast Read Access Time: 45/55/70/90 ns
s
Low Power CMOS Dissipation:
Licensed Intel
second source
s
64K x 16 Word Organization
s
Stop Timer for Program/Erase
s
On-Chip Address and Data Latches
s
JEDEC Standard Pinouts:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100
µ
A max (CMOS levels)
s
High Speed Programming:
–10
µ
s per byte
–1 Sec Typ Chip Program
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s
100,000 Program/Erase Cycles
s
10 Year Data Retention
s
Electronic Signature
s
0.5 Seconds Typical Chip-Erase
s
12.0V
±
5% Programming and Erase Voltage
s
Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
2
PROM devices. Programming and Erase
are performed through an operation and verify algo-
rithm. The instructions are input via the I/O bus, using a
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
I/O0–I/O15
BLOCK DIAGRAM
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
1,048,576-BIT
MEMORY
ARRAY
A0–A15
X-DECODER
VOLTAGE VERIFY
SWITCH
28F101-1
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
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