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CAT28C257HNI-15T

Description
256K-Bit CMOS PARALLEL E2PROM
Categorystorage    storage   
File Size54KB,10 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT28C257HNI-15T Overview

256K-Bit CMOS PARALLEL E2PROM

CAT28C257HNI-15T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFJ
package instructionQCCJ,
Contacts32
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time150 ns
Other features100000 PROGRAM/ERASE CYCLES; DATA RETENTION = 100 YEARS
Data retention time - minimum100
JESD-30 codeR-PQCC-J32
JESD-609 codee0
length13.97 mm
memory density262144 bi
Memory IC TypeEEPROM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height3.55 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width11.43 mm
Base Number Matches1
Advanced
CAT28C257
256K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
Fast Read Access Times: 90/120/150 ns
s
Low Power CMOS Dissipation:
s
Automatic Page Write Operation:
–Active: 25 mA Max.
–Standby: 150
µ
A Max.
s
Simple Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s
End of Write Detection:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
–Toggle Bit
–DATA Polling
DATA
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial and Automotive
–5ms Max
s
CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C257 is a fast, low power, 5V-only CMOS
Parallel E
2
PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware.
DATA
Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C257 features
hardware and software write protection.
The CAT28C257 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
32,768 x 8
E
2
PROM
ARRAY
128 BYTE PAGE
REGISTER
A7–A14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5096 FHD F02
I/O0–I/O7
A0–A6
ADDR. BUFFER
& LATCHES
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25073-00 2/98
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Index Files: 1135  2642  1886  92  1121  23  54  38  2  44 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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