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5962G9651801QCC

Description
AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size220KB,9 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962G9651801QCC Overview

AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

5962G9651801QCC Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionDIP,
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-CDIP-T14
JESD-609 codee4
Logic integrated circuit typeAND GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)13 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose500k Rad(Si) V
width7.62 mm
Base Number Matches1
Standard Products
UT54ACS08/UT54ACTS08
Quadruple 2-Input AND Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS08 - SMD 5962-96518
UT54ACTS08 - SMD 5962-96519
DESCRIPTION
The UT54ACS08 and the UT54ACTS08 are quadruple two-
input AND gates. The circuits perform the Boolean functions
Y= A
B or Y = A + B
in positive logic.
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
14-Pin Flatpack
Top View
A1
B1
Y1
A2
B2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUT
A
H
L
X
B
H
X
L
OUTPUT
Y
H
L
L
Y2
V
SS
LOGIC DIAGRAM
A1
B1
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
&
(3)
(6)
(8)
Y1
Y2
Y3
Y4
Y1
A2
B2
A3
B3
A4
B4
Y2
Y3
Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
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