74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Features
s
Broadside pinout allows for easy board layout
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT18823SSC
74ACT18823MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
CLR
n
EN
n
CP
n
I
0
–I
17
O
0
–O
17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500294
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74ACT18823
Functional Description
The ACT18823 consists of eighteen D-type edge-triggered
flip-flops. These have 3-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
device is byte controlled with each byte functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The follow-
ing description applies to each byte. The buffered clock
(CP
n
) and buffered Output Enable (OE
n
) are common to all
flip-flops within that byte. The flip-flops will store the state
of their individual D inputs that meet set-up and hold time
requirements on the LOW-to-HIGH CP
n
transition. With
OE
n
LOW, the contents of the flip-flops are available at the
outputs. When OE
n
is HIGH, the outputs go to the imped-
ance state. Operation of the OE
n
input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR
n
) and Clock Enable
(EN
n
) pins. These devices are ideal for parity bus interfac-
ing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
Inputs
OE CLR
H
H
H
L
H
L
H
H
L
L
X
X
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
CP
Internal Output
X
X
X
I
n
L
H
X
X
X
X
L
H
L
H
Q
L
H
L
L
NC
NC
L
H
L
H
O
n
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
X
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
=
LOW-to-HIGH Transition
NC= No Change
Note 1:
The table represents the logic for one byte. The two bytes are inde-
pendent of each other and function identically.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
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2
74ACT18823
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin
Junction Temperature
PDIP/SOIC
Storage Temperature
+140°C
−65°C
to
+150°C
±
50 mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±
50 mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 4)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−0.1V
V
OUT
=
0.1V
or V
CC
−0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 3)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 3)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
, GND
V
I
=
V
CC
−2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
Note 3:
All outputs loaded; thresholds associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT18823
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 5)
f
MAX
Maximum Clock
5.0
Frequency
t
PHL
t
PLH
t
PHL
Propagation Delay
5.0
CP
n
to O
n
Propagation Delay
5.0
CLR
n
to O
n
t
PZL
t
PZH
t
PLZ
t
PHZ
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
Min
100
2.0
2.0
2.0
2.0
9.0
9.0
9.0
9.0
9.0
7.0
8.0
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
90
2.0
2.0
2.0
2.0
2.0
1.5
1.5
9.5
ns
9.5
9.5
10.0
ns
10.0
7.5
ns
8.5
ns
Max
MHz
Units
Output Enable Time
5.0
2.0
Output Disable Time
5.0
1.5
1.5
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 6)
t
S
Setup Time, HIGH or LOW,
5.0
Input to Clock
t
H
Hold Time, HIGH or LOW,
5.0
Input to Clock
t
S
Setup Time, HIGH or LOW,
5.0
Enable to Clock
t
H
Hold Time, HIGH or LOW,
5.0
Enable to Clock
t
W
CP
n
Pulse Width,
HIGH or LOW
t
W
CLR
n
Pulse Width,
HIGH or LOW
t
rec
Recovery Time,
5.0
CLR
n
to CP
n
Note 6:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Units
Guaranteed Minimum
3.0
3.0
ns
1.5
1.5
ns
3.0
3.0
ns
1.5
1.5
ns
5.0
4.0
4.0
ns
5.0
4.0
4.0
ns
6.0
6.0
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
95
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
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4
74ACT18823
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
5
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