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74ACT18823MTD

Description
18-Bit D-Type Flip-Flop with 3-STATE Outputs
Categorylogic    logic   
File Size62KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74ACT18823MTD Overview

18-Bit D-Type Flip-Flop with 3-STATE Outputs

74ACT18823MTD Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP56,.3,20
Contacts56
Reach Compliance Codeunknow
seriesACT
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
Maximum Frequency@Nom-Su90000000 Hz
MaximumI(ol)0.024 A
Humidity sensitivity level2
Number of digits9
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply5 V
propagation delay (tpd)9.5 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width6.1 mm
Base Number Matches1
74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Features
s
Broadside pinout allows for easy board layout
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT18823SSC
74ACT18823MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
CLR
n
EN
n
CP
n
I
0
–I
17
O
0
–O
17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500294
www.fairchildsemi.com

74ACT18823MTD Related Products

74ACT18823MTD 74ACT18823 74ACT18823SSC
Description 18-Bit D-Type Flip-Flop with 3-STATE Outputs 18-Bit D-Type Flip-Flop with 3-STATE Outputs 18-Bit D-Type Flip-Flop with 3-STATE Outputs
Is it Rohs certified? conform to - conform to
Maker Fairchild - Fairchild
Parts packaging code TSSOP - SSOP
package instruction TSSOP, TSSOP56,.3,20 - SSOP, SSOP56,.4
Contacts 56 - 56
Reach Compliance Code unknow - compli
series ACT - ACT
JESD-30 code R-PDSO-G56 - R-PDSO-G56
JESD-609 code e3 - e3
length 14 mm - 18.415 mm
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type BUS DRIVER - BUS DRIVER
Maximum Frequency@Nom-Su 90000000 Hz - 90000000 Hz
MaximumI(ol) 0.024 A - 0.024 A
Humidity sensitivity level 2 - 1
Number of digits 9 - 9
Number of functions 2 - 2
Number of ports 2 - 2
Number of terminals 56 - 56
Maximum operating temperature 85 °C - 85 °C
Minimum operating temperature -40 °C - -40 °C
Output characteristics 3-STATE - 3-STATE
Output polarity TRUE - TRUE
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code TSSOP - SSOP
Encapsulate equivalent code TSSOP56,.3,20 - SSOP56,.4
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 - 260
power supply 5 V - 5 V
propagation delay (tpd) 9.5 ns - 9.5 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 1.2 mm - 2.74 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V
surface mount YES - YES
technology CMOS - CMOS
Temperature level INDUSTRIAL - INDUSTRIAL
Terminal surface Matte Tin (Sn) - Matte Tin (Sn)
Terminal form GULL WING - GULL WING
Terminal pitch 0.5 mm - 0.635 mm
Terminal location DUAL - DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
Trigger type POSITIVE EDGE - POSITIVE EDGE
width 6.1 mm - 7.5 mm
Base Number Matches 1 - 1
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