74ACT20
DUAL 4-INPUT NAND GATE
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT20B
74ACT20M
DESCRIPTION
The 74ACT20 is an advanced high-speed CMOS
DUAL 4-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
The internal circuit is composed of 3 stages in-
cluding buffer output, which enables high noise
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
r
P
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s)
t(
bs
-O
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
et
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T&R
74ACT20MTR
74ACT20TTR
April 2001
1/8
74ACT20
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 9
2, 10
3, 11
5, 13
6, 8
7
14
SYMBOL
1A to 2A
1B to 2B
1C to 2C
1C to 2D
1Y to 2Y
GND
V
CC
NAME AND FUNCTION
Data Inputs
Data Inputs
Data Inputs
Data Inputs
Data Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
A
L
X
X
X
H
X : Don’t Care
B
X
L
X
X
H
C
X
X
L
X
H
D
X
X
X
L
H
Y
H
H
H
H
L
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter²
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
O
so
b
V
CC
V
I
V
O
T
op
dt/dv
te
le
r
P
uc
od
s)
t(
bs
-O
et
l
o
P
e
od
r
Value
±
20
±
20
±
50
±
100
s)
t(
uc
Unit
V
V
V
mA
mA
mA
mA
°C
°C
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
-65 to +150
300
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
-55 to 125
8
Unit
V
V
V
°C
ns/V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperqture
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
1) V
IN
from 0.8V to 2.0V
2/8
74ACT20
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Low Level Output
Voltage
4.5
5.5
4.5
5.5
I
I
I
CCT
I
CC
I
OLD
I
OHD
Input Leakage Cur-
rent
Max I
CC
/Input
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
5.5
5.5
5.5
5.5
V
O
= 0.1 V or
V
CC
-0.1V
V
O
= 0.1 V or
V
CC
-0.1V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=50
µA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
- 2.1V
V
I
= V
CC
or GND
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
0.6
4
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±
0.1
T
A
= 25°C
Min.
2.0
2.0
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Max.
Value
-40 to 85°C
Min.
2.0
2.0
0.8
0.8
4.4
5.4
3.7
4.7
0.1
0.1
V
Max.
-55 to 125°C
Min.
2.0
2.0
0.8
0.8
V
Max.
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
t
PLH
t
PHL
Propagation Delay
Time
(*) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
O
so
b
Symbol
C
IN
C
PD
te
le
r
P
uc
od
5.0
(*)
V
CC
(V)
5.0
5.0
V
CC
(V)
s)
t(
bs
-O
Min.
1.5
l
o
te
e
r
P
od
1.5
40
75
-75
±
1
s)
t(
uc
0.5
0.5
±
1
1.6
80
50
-50
µA
mA
µA
mA
mA
Value
-40 to 85°C
Min.
1.0
Max.
9.5
-55 to 125°C
Min.
1.0
Max.
9.5
ns
Unit
T
A
= 25°C
Typ.
5.0
Max.
7.2
Test Condition
T
A
= 25°C
Min.
Typ.
3.8
f
IN
= 10MHz
33
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
Parameter
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per gate)
3/8
74ACT20
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
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P
e
od
r
s)
t(
uc
4/8
FPGA/CPLD
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