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74ACT20TTR

Description
DUAL 4-INPUT NAND GATE
Categorylogic    logic   
File Size184KB,8 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric Compare View All

74ACT20TTR Overview

DUAL 4-INPUT NAND GATE

74ACT20TTR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSTMicroelectronics
Parts packaging codeTSSOP
package instructionTSSOP-14
Contacts14
Reach Compliance Code_compli
seriesACT
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.024 A
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Prop。Delay @ Nom-Su9.5 ns
propagation delay (tpd)9.5 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
74ACT20
DUAL 4-INPUT NAND GATE
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT20B
74ACT20M
DESCRIPTION
The 74ACT20 is an advanced high-speed CMOS
DUAL 4-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
The internal circuit is composed of 3 stages in-
cluding buffer output, which enables high noise
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
et
l
o
P
e
od
r
s)
t(
uc
T&R
74ACT20MTR
74ACT20TTR
April 2001
1/8

74ACT20TTR Related Products

74ACT20TTR 74ACT20 74ACT20B 74ACT20M
Description DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE
Is it Rohs certified? incompatible - conform to conform to
Parts packaging code TSSOP - DIP SOIC
package instruction TSSOP-14 - DIP, DIP14,.3 SOP, SOP14,.25
Contacts 14 - 14 14
Reach Compliance Code _compli - compli compli
series ACT - ACT ACT
JESD-30 code R-PDSO-G14 - R-PDIP-T14 R-PDSO-G14
JESD-609 code e0 - e3 e4
Load capacitance (CL) 50 pF - 50 pF 50 pF
Logic integrated circuit type NAND GATE - NAND GATE NAND GATE
MaximumI(ol) 0.024 A - 0.024 A 0.024 A
Number of functions 2 - 2 2
Number of entries 4 - 4 4
Number of terminals 14 - 14 14
Maximum operating temperature 125 °C - 125 °C 125 °C
Minimum operating temperature -55 °C - -55 °C -55 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP - DIP SOP
Encapsulate equivalent code TSSOP14,.25 - DIP14,.3 SOP14,.25
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - IN-LINE SMALL OUTLINE
method of packing TAPE AND REEL - TUBE TUBE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
power supply 5 V - 5 V 5 V
Prop。Delay @ Nom-Su 9.5 ns - 9.5 ns 9.5 ns
propagation delay (tpd) 9.5 ns - 9.5 ns 9.5 ns
Certification status Not Qualified - Not Qualified Not Qualified
Schmitt trigger NO - NO NO
Maximum seat height 1.1 mm - 5.1 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V 5 V
surface mount YES - NO YES
technology CMOS - CMOS CMOS
Temperature level MILITARY - MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) - Matte Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING - THROUGH-HOLE GULL WING
Terminal pitch 0.65 mm - 2.54 mm 1.27 mm
Terminal location DUAL - DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
width 4.4 mm - 7.62 mm 3.9 mm

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