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74ACT280M

Description
9 BIT PARITY GENERATOR/CHECKER
Categorylogic    logic   
File Size60KB,8 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74ACT280M Overview

9 BIT PARITY GENERATOR/CHECKER

74ACT280M Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codecompli
seriesACT
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Logic integrated circuit typePARITY GENERATOR/CHECKER
Humidity sensitivity level1
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply5 V
propagation delay (tpd)14.5 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
Base Number Matches1
®
74ACT280
9 BIT PARITY GENERATOR/CHECKER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT280B
74ACT280M
nine data inputs control the output conditions.
When the number of high level input is odd,
ΣODD
output is kept high and
ΣEVEN
output low.
Conservely, when the output is even,
Σ
EVEN
output is kept high and
ΣODD
low.
The IC generates either odd or even parity
making it flexible application.
The word-length capability is easily expanded by
cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The AC280 is an advanced high-speed CMOS 9
BIT PARITY GENERATOR - CHECKER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (
Σ
ODD and
Σ
EVEN). The
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
1/8

74ACT280M Related Products

74ACT280M 74ACT280B 74ACT280
Description 9 BIT PARITY GENERATOR/CHECKER 9 BIT PARITY GENERATOR/CHECKER 9 BIT PARITY GENERATOR/CHECKER
Is it Rohs certified? conform to conform to -
Maker STMicroelectronics STMicroelectronics -
Parts packaging code SOIC DIP -
package instruction SOP, SOP14,.25 DIP, DIP14,.3 -
Contacts 14 14 -
Reach Compliance Code compli compli -
series ACT ACT -
JESD-30 code R-PDSO-G14 R-PDIP-T14 -
JESD-609 code e4 e3 -
Logic integrated circuit type PARITY GENERATOR/CHECKER PARITY GENERATOR/CHECKER -
Number of digits 9 9 -
Number of functions 1 1 -
Number of terminals 14 14 -
Maximum operating temperature 125 °C 125 °C -
Minimum operating temperature -55 °C -55 °C -
Output polarity COMPLEMENTARY COMPLEMENTARY -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code SOP DIP -
Encapsulate equivalent code SOP14,.25 DIP14,.3 -
Package shape RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE IN-LINE -
Peak Reflow Temperature (Celsius) 260 NOT SPECIFIED -
power supply 5 V 5 V -
propagation delay (tpd) 14.5 ns 14.5 ns -
Certification status Not Qualified Not Qualified -
Maximum seat height 1.75 mm 5.1 mm -
Maximum supply voltage (Vsup) 5.5 V 5.5 V -
Minimum supply voltage (Vsup) 4.5 V 4.5 V -
Nominal supply voltage (Vsup) 5 V 5 V -
surface mount YES NO -
technology CMOS CMOS -
Temperature level MILITARY MILITARY -
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn) -
Terminal form GULL WING THROUGH-HOLE -
Terminal pitch 1.27 mm 2.54 mm -
Terminal location DUAL DUAL -
Maximum time at peak reflow temperature 30 NOT SPECIFIED -
width 3.9 mm 7.62 mm -
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