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74ACT280B

Description
9 BIT PARITY GENERATOR/CHECKER
Categorylogic    logic   
File Size60KB,8 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74ACT280B Overview

9 BIT PARITY GENERATOR/CHECKER

74ACT280B Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codecompli
seriesACT
JESD-30 codeR-PDIP-T14
JESD-609 codee3
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)14.5 ns
Certification statusNot Qualified
Maximum seat height5.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
®
74ACT280
9 BIT PARITY GENERATOR/CHECKER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT280B
74ACT280M
nine data inputs control the output conditions.
When the number of high level input is odd,
ΣODD
output is kept high and
ΣEVEN
output low.
Conservely, when the output is even,
Σ
EVEN
output is kept high and
ΣODD
low.
The IC generates either odd or even parity
making it flexible application.
The word-length capability is easily expanded by
cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The AC280 is an advanced high-speed CMOS 9
BIT PARITY GENERATOR - CHECKER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (
Σ
ODD and
Σ
EVEN). The
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
1/8

74ACT280B Related Products

74ACT280B 74ACT280 74ACT280M
Description 9 BIT PARITY GENERATOR/CHECKER 9 BIT PARITY GENERATOR/CHECKER 9 BIT PARITY GENERATOR/CHECKER
Is it Rohs certified? conform to - conform to
Maker STMicroelectronics - STMicroelectronics
Parts packaging code DIP - SOIC
package instruction DIP, DIP14,.3 - SOP, SOP14,.25
Contacts 14 - 14
Reach Compliance Code compli - compli
series ACT - ACT
JESD-30 code R-PDIP-T14 - R-PDSO-G14
JESD-609 code e3 - e4
Logic integrated circuit type PARITY GENERATOR/CHECKER - PARITY GENERATOR/CHECKER
Number of digits 9 - 9
Number of functions 1 - 1
Number of terminals 14 - 14
Maximum operating temperature 125 °C - 125 °C
Minimum operating temperature -55 °C - -55 °C
Output polarity COMPLEMENTARY - COMPLEMENTARY
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code DIP - SOP
Encapsulate equivalent code DIP14,.3 - SOP14,.25
Package shape RECTANGULAR - RECTANGULAR
Package form IN-LINE - SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - 260
power supply 5 V - 5 V
propagation delay (tpd) 14.5 ns - 14.5 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 5.1 mm - 1.75 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V
surface mount NO - YES
technology CMOS - CMOS
Temperature level MILITARY - MILITARY
Terminal surface Matte Tin (Sn) - Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form THROUGH-HOLE - GULL WING
Terminal pitch 2.54 mm - 1.27 mm
Terminal location DUAL - DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - 30
width 7.62 mm - 3.9 mm

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