Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger
actions
•
Multiple input enable for easy
expansion
•
Ideal for memory chip select
decoding
•
Inputs accept voltages higher than
V
CC
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
DESCRIPTION
74AHC138;
74AHCT138
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT138 decoders accept three binary weighted address inputs
(A
0
, A
1
and A
2
) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y
0
to Y
7
).
The ‘138’ features three enable inputs: two active LOW (E
1
and E
2
) and one
active HIGH (E
3
). Every output will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the ‘138’ to a
1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.
The ‘138’ can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
The ‘138’ is identical to the ‘238’ but has inverting outputs.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay A
n
to Y
n
propagation delay E
3
to Y
n
; E
n
to Y
n
input capacitance
output capacitance
power dissipation capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
4.4
4.2
3.0
4.0
18
AHCT
4.4
4.3
3.0
4.0
23
ns
ns
pF
pF
pF
UNIT
1999 Sep 27
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FUNCTION TABLE
See note 1.
INPUT
E
1
H
X
X
L
L
L
L
L
L
L
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC138D
74AHC138PW
74AHCT138D
74AHCT138PW
PINNING
PIN
1, 2 and 3
4 and 5
6
7, 9, 10 11, 12, 13, 14 and 15
8
16
SYMBOL
A
0
, A
1
and A
2
E
1
and E
2
E
3
Y
7
to Y
0
GND
V
CC
address inputs
enable inputs (active LOW)
enable input (active HIGH)
outputs (active LOW)
ground (0 V)
DC supply voltage
PACKAGES
NORTH AMERICA
PINS
74AHC138D
74AHC138PW DH
74AHCT138D
74AHCT138PW DH
16
16
16
16
PACKAGE
SO
TSSOP
SO
TSSOP
E
2
X
H
X
L
L
L
L
L
L
L
L
E
3
X
X
L
H
H
H
H
H
H
H
H
A
0
X
X
X
L
H
L
H
L
H
L
H
A
1
X
X
X
L
L
H
H
L
L
H
H
A
2
X
X
X
L
L
L
L
H
H
H
H
Y
0
H
H
H
L
H
H
H
H
H
H
H
Y
1
H
H
H
H
L
H
H
H
H
H
H
Y
2
H
H
H
H
H
L
H
H
H
H
H
OUTPUT
Y
3
H
H
H
H
H
H
L
H
H
H
H
Y
4
H
H
H
H
H
H
H
L
H
H
H
74AHC138;
74AHCT138
Y
5
H
H
H
H
H
H
H
H
L
H
H
Y
6
H
H
H
H
H
H
H
H
H
L
H
Y
7
H
H
H
H
H
H
H
H
H
H
L
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT109-1
SOT403-1
SOT109-1
SOT403-1
DESCRIPTION
1999 Sep 27
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient temperature
range
see DC and AC
characteristics per
device
V
CC
= 5 V
±0.5
V
CONDITIONS
MIN.
2.0
0
0
−40
−40
TYP. MAX. MIN.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
4.5
0
0
−40
74AHC138;
74AHCT138
74AHCT
UNIT
TYP. MAX.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
V
V
V
°C
+125
−40
100
20
−
−
+125
°C
−
20
ns/V
t
r
,t
f
(∆t/∆f) input rise and fall rates
V
CC
= 3.3 V
±0.3
V
−
−
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
°C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
°C
the value of P
D
derates linearly with 5.5 mW/K.
PARAMETER
DC supply voltage
input voltage range
DC input diode current
DC output diode current
DC V
CC
or GND current
storage temperature range
power dissipation per package
for temperature range:
−40
to +125
°C;
note 2
V
I
<
−0.5
V; note 1
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V; note 1
CONDITIONS
MIN. MAX. UNIT
−0.5
−0.5
−
−
−
−
−65
−
+7.0
+7.0
−20
±20
±25
±75
500
V
V
mA
mA
mA
mA
mW
DC output source or sink current
−0.5
V < V
O
< V
CC
+ 0.5 V
+150
°C
1999 Sep 27
5
FPGA/CPLD
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