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74AHC1G09GW

Description
AND Gate, CMOS, PDSO5
Categorylogic    logic   
File Size56KB,11 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Environmental Compliance
Download Datasheet Parametric View All

74AHC1G09GW Overview

AND Gate, CMOS, PDSO5

74AHC1G09GW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instructionTSSOP, TSSOP5/6,.08
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G5
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
MaximumI(ol)0.008 A
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-DRAIN
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP5/6,.08
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply2/5.5 V
Prop。Delay @ Nom-Sup12.5 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Base Number Matches1
74AHC1G09
2-input AND gate with open-drain output
Rev. 01 — 26 September 2005
Product data sheet
1. General description
The 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain
outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH level.
2. Features
s
High noise immunity
s
ESD protection:
x
HBM JESD22-A114-C exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Low power dissipation
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C.
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
3.0 ns.
Symbol
t
PZL
, t
PLZ
C
i
C
PD
[1]
Parameter
propagation delay
A and B to Y
input capacitance
power dissipation
capacitance
Conditions
V
CC
= 4.5 V to 5.5 V;
C
L
= 15 pF
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[1]
Min
-
-
-
Typ
3.2
1.5
5
Max
5.5
10
-
Unit
ns
pF
pF
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N + (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
(C
L
×
V
CC2
×
f
o
) = dissipation due to the output if the combination of the pull up voltage and resistance
results in V
CC
at the output.
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