Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
FEATURES
•
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
DESCRIPTION
The 74ALVT16823 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ALVT16823 has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
It is designed for V
CC
operation from 2.5 V to 3.0 V with I/O
compatibility to 5 V.
•
5V I/O Compatible
•
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•
Live insertion/extraction permitted
•
Power-up 3-State
•
Power-up Reset
•
No bus current loading when output is tied to 5 V bus
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF
V
I
= 0V or V
CC
V
I/O
= 0V or 3.0V
Outputs disabled
TYPICAL
UNIT
2.5V
2.5
3
9
40
3.3V
1.9
3
9
70
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16823 DL
74ALVT16823 DGG
NORTH AMERICA
AV16823 DL
AV16823 DGG
DWG NUMBER
SOT371–1
SOT364–1
PIN DESCRIPTION
PIN NUMBER
2, 27
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
56, 29
55, 30
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1OE, 2OE
1D0-1D8
2D0-2D8
1Q0-1Q8
2Q0-2Q8
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
V
CC
FUNCTION
Output enable input (active-Low)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
Positive supply voltage
1998 Jun 12
2
853-2069 19558
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
nMR
L
H
H
H
nCE
X
L
L
H
nCP
X
↑
↑
↑
nDx
X
h
l
X
OUTPUTS
nQ0 – nQ8
L
H
L
NC
Hold
High impedance
Clear
Load and read data
OPERATING MODE
H
X
X
X
X
Z
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
V
CC
Data Input
To internal circuit
SW00044
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
PARAMETER
DC supply voltage
DC input diode current
DC input
voltage
3
V
O
< 0
Output in Off or High state
Output in Low state
Output in High state
voltage
3
DC output diode current
DC output
V
I
< 0
CONDITIONS
RATING
-0.5 to +4.6
-50
-0.5 to +7.0
-50
-0.5 to +7.0
128
-64
UNIT
V
mA
V
mA
V
mA
DC output current
T
stg
Storage temperature range
-65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
1998 Jun 12
4
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
2.5V RANGE LIMITS
MIN
2.3
0
1.7
0.7
–8
8
24
10
+85
–40
MAX
2.7
5.5
3.3V RANGE LIMITS
MIN
3.0
0
2.0
0.8
–32
32
64
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS (3.3V
"0.3V
RANGE)
LIMITS
SYMBOL
V
IK
V
OH
PARAMETER
Input clamp voltage
High-level out ut voltage
output
TEST CONDITIONS
V
CC
= 3.0V; I
IK
= –18mA
V
CC
= 3 0 to 3 6V; I
OH
= –100µA
3.0 3.6V;
V
CC
= 3.0V; I
OH
= –32mA
V
CC
= 3 0V; I
OL
= 100µA
3.0V;
V
OL
Low-level out ut voltage
output
V
CC
= 3.0V; I
OL
= 16mA
V
CC
= 3.0V; I
OL
= 32mA
V
CC
= 3.0V; I
OL
= 64mA
V
RST
Power-up output low voltage
6
V
CC
= 3.6V; I
O
= 1mA; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
or GND
I
I
In ut
Input leakage current
V
CC
= 0 or 3.6V; V
I
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0V
I
OFF
I
HOLD
Off current
Bus Hold current
D inputs
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State output
current
3
3-State output High current
3-State output Low current
Quiescent supply current
Additional supply current per
input pin
2
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
I
= 0V to 3.6V; V
CC
= 3.6V
7
V
O
= 5.5V; V
CC
= 3.0V
V
CC
≤
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
OE/OE = Don’t care
V
CC
= 3.6V; V
O
= 3.0V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
5
V
CC
= 3V to 3.6V; One input at V
CC
–0.6V,
Other inputs at V
CC
or GND
75
–75
±500
10
1
0.5
0.5
0.06
3.9
0.06
0.04
125
±100
5
–5
0.1
5.5
0.1
0.4
mA
mA
µA
µA
µA
µA
Data pins
4
ins
Control pins
0.1
0.1
0.5
0.1
0.1
130
–140
µA
V
CC
–0 2
–0.2
2.0
Temp = -40°C to +85°C
MIN
TYP
1
–0.85
V
CC
2.3
0 07
0.07
0.25
0.3
0.4
02
0.2
0.4
0.5
0.55
0.55
±1
10
1
-5
±100
µA
µA
V
V
MAX
–1.2
V
V
UNIT
I
EX
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
∆I
CC
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
0.3V a
transition time of 100µsec is permitted. This parameter is valid for T
amb
= 25°C only.
4. Unused pins at V
CC
or GND.
5. I
CCZ
is measured with outputs pulled up to V
CC
or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Jun 12
5
Embedded System
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