74F113PC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> 74F113PC

74F113PC: DescriptionDual J-K negative edge-triggered flip-flops without reset; Categorylogic logic; File Size61KB，6 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

Download Datasheet Parametric Compare View All

74F113PC Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	74F113PC	-	-	View	Buy Now

74F113PC Overview

Dual J-K negative edge-triggered flip-flops without reset

74F113PC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	unknow
series	F/FAST
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.18 mm
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Su	80000000 Hz
MaximumI(ol)	0.02 A
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	19 mA
propagation delay (tpd)	7 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	80 MHz
Base Number Matches	1

Preview

Download Datasheet

View All

74F113 Dual JK Negative Edge-Triggered Flip-Flop

April 1988

Revised July 1999

74F113

Dual JK Negative Edge-Triggered Flip-Flop

General Description

The 74F113 offers individual J, K, Set and Clock inputs.

When the clock goes HIGH the inputs are enabled and

data may be entered. The logic level of the J and K inputs

may be changed when the clock pulse is HIGH and the flip-

flop will perform according to the Truth Table as long as

minimum setup and hold times are observed. Input data is

transferred to the outputs on the falling edge of the clock

pulse.

Asynchronous input:

LOW input to S

sets Q to HIGH level

Set is independent of clock

Ordering Code:

Order Number

74F113SC

74F113SJ

74F113PC

Package Number

M14A

M14D

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009473

www.fairchildsemi.com

74F113PC Related Products

	74F113PC	74F113	74F113SJ	74F113SC
Description	Dual J-K negative edge-triggered flip-flops without reset	Dual J-K negative edge-triggered flip-flops without reset	Dual J-K negative edge-triggered flip-flops without reset	Dual J-K negative edge-triggered flip-flops without reset
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	Fairchild	-	Fairchild	Fairchild
Parts packaging code	DIP	-	SOIC	SOIC
package instruction	DIP, DIP14,.3	-	SOP, SOP14,.3	SOP, SOP14,.25
Contacts	14	-	14	14
Reach Compliance Code	unknow	-	unknown	unknow
series	F/FAST	-	F/FAST	F/FAST
JESD-30 code	R-PDIP-T14	-	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e0	-	e0	e0
length	19.18 mm	-	10.2 mm	8.65 mm
Logic integrated circuit type	J-K FLIP-FLOP	-	J-K FLIP-FLOP	J-K FLIP-FLOP
MaximumI(ol)	0.02 A	-	0.02 A	0.02 A
Number of digits	2	-	2	2
Number of functions	2	-	2	2
Number of terminals	14	-	14	14
Maximum operating temperature	70 °C	-	70 °C	70 °C
Output polarity	COMPLEMENTARY	-	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	-	SOP	SOP
Encapsulate equivalent code	DIP14,.3	-	SOP14,.3	SOP14,.25
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	-	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	-	5 V	5 V
Maximum supply current (ICC)	19 mA	-	19 mA	19 mA
propagation delay (tpd)	7 ns	-	7 ns	7 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	-	2.1 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	-	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	-	5 V	5 V
surface mount	NO	-	YES	YES
technology	TTL	-	TTL	TTL
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	GULL WING	GULL WING
Terminal pitch	2.54 mm	-	1.27 mm	1.27 mm
Terminal location	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
Trigger type	NEGATIVE EDGE	-	NEGATIVE EDGE	NEGATIVE EDGE
width	7.62 mm	-	5.3 mm	3.9 mm
minfmax	80 MHz	-	80 MHz	80 MHz
Base Number Matches	1	-	1	1

Recommended Resources

MC-1590 IF amplifier circuit diagram

Internal structure of quad voltage comparator LM339 and voltage comparator LM393b

Diode, resistance and capacitance spark elimination circuit a

C1160 heavy lathe electrical control circuit schematic circuit

Protection circuit diagram using Zener diode VDW1

Simple noise meter

What are the difficulties and common methods of battery SOC estimation?: [i=s]This post was last edited by qwqwqw2088 on 2019-9-10 10:41[/i]Electric vehicles have gone from a range of 400 kilometers to 300 kilometers, and mobile phones have gone from charging once every tw...; qwqwqw2088 Energy Infrastructure?

Circuit Design of Special Integrated Switching Power Supply: Abstract: The performance characteristics, circuit design schemes and application fields of four new special integrated switching power supplies are described in detail.Keywords: Special integrated sw...; zbz0529 Power technology

VC++ In-depth Explanation (Revised Edition): "VC++ In-depth Explanation (Revised Edition)" starts with practical applications, and gradually explains the internal operating mechanism of Windows programs, MFC framework, text, menus, dialog boxes,...; arui1999 Download Centre

Proteus8.6 simulation example of STM32F103: Use STM32Cube to create an MDK example to control the PC13 flashing light, and use the STM32F103C8T8 core board for verification. [code] while (1) { /* USER CODE END WHILE */ HAL_GPIO_TogglePin(LED_GP...; dcexpert stm32/stm8

eZ430-RF2500 Development Tools: Texas Instruments' eZ430 -RF 2500 development kit consists of two USB-drive-sized development boards that can connect wirelessly to each other (Figure 4). Wireless connectivity appeals to me because I...; sdjntl Microcontroller MCU

【NXP Rapid IoT Review】+ Summary: I was fortunate to have conducted an evaluation of the "NXP Rapid IoT Prototyping Kit". I personally feel that the evaluation is not in-depth and extensive enough. I hope that after the event, the kit...; anananjjj RF/Wirelessly

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components