87320-428HLF datasheet, PDF - EEWORLD Datasheet

87320-428HLF: DescriptionBoard Connector, 28 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle, LEAD FREE; CategoryThe connector The connector; File Size150KB，2 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/; Environmental Compliance

Download Datasheet Parametric View All

87320-428HLF Overview

Board Connector, 28 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle, LEAD FREE

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Amphenol
package instruction	LEAD FREE
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	LATCHED
body width	0.303 inch
subject depth	0.386 inch
body length	1.4 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	NOT SPECIFIED
Contact completed and terminated	Tin (Sn) - with Nickel (Ni) barrier
Contact point gender	MALE
Contact material	NOT SPECIFIED
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
DIN compliance	NO
Filter function	NO
IEC compliance	NO
Insulator color	BLACK
insulator material	GLASS FILLED PCT
JESD-609 code	e3
MIL compliance	NO
Manufacturer's serial number	87320
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Mixed contacts	NO
Installation option 1	LOCKING
Installation method	STRAIGHT
Installation type	BOARD
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
Options	GENERAL PURPOSE
PCB contact pattern	RECTANGULAR
PCB contact row spacing	2.54 mm
Plating thickness	100u inch
Guideline	UL
reliability	COMMERCIAL
Terminal length	0.12 inch
Terminal pitch	2.54 mm
Termination type	SOLDER
Total number of contacts	28
UL Flammability Code	94V-0
Base Number Matches	1

PDM: Rev:F

STATUS:

Released

Printed: Nov 03, 2010

New DDS+PLL Clock Generator Based on FPGA: Document description: Based on the characteristics of direct digital frequency synthesis (DDS) and integrated phase-locked loop (PLL) technology, a new DDS-excited PLL system frequency synthesis clock...; 五月一 FPGA/CPLD

Looking for the delay program in open at.: I want the delay program in open at. And how is it implemented......; 68872401 Embedded System

Can supercapacitors accelerate cars?: The advent of supercapacitors has made people curious about its "super" features, what exactly makes it super, and in what fields can its "super" be demonstrated. Supercapacitors play a significant ro...; BIGCAP Energy Infrastructure?

There are two questions about the frequency division circuit, as shown in the figure: There are two questions about the frequency division circuit, as shown in the figure...; QWE4562009 Analog electronics

【Altera SoC Experience Tour】+ Running a complete convolutional neural network on DE1: [i=s]This post was last edited by zhaoyongke on 2015-5-30 17:53[/i] It's been a while since I last posted. I've been debugging another Stratix V board. Enough of small talk, here's the latest progress...; zhaoyongke FPGA/CPLD

【Uncle T's Library】Freescale K60 related albums: [i=s]This post was last edited by tyw on 2017-11-13 11:58[/i] [url=https://download.eeworld.com.cn/detail/tyw/565858]K60-AD.DA.CMP.TSI Module[/url] [url=https://download.eeworld.com.cn/detail/tyw/5658...; tyw Download Centre

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components