74F398 • 74F399 Quad 2-Port Register
April 1988
Revised August 1999
74F398 • 74F399
Quad 2-Port Register
General Description
The 74F398 and 74F399 are the logical equivalents of a
quad 2-input multiplexer feeding into four edge-triggered
flip-flops. A common Select input determines which of the
two 4-bit words is accepted. The selected data enters the
flip-flops on the rising edge of the clock. The 74F399 is the
16-pin version of the 74F398, with only the Q outputs of the
flip-flops available.
Features
s
Select inputs from two data sources
s
Fully positive edge-triggered operation
s
Both true and complement outputs—74F398
Ordering Code:
Order Number
74F398SC
74F398PC
74F399SC
74F399SJ
74F399PC
Package Number
M20B
N20A
M16A
M16D
N16E
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
74F398
74F399
© 1999 Fairchild Semiconductor Corporation
DS009533
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74F398 • 74F399
Logic Symbols
74F398
74F398
74F399
74F399
IEEE/IEC
Unit Loading/Fan Out
U.L.
Pin Names
S
CP
I
0a
–I
0d
I
1a
–I
1d
Q
a
–Q
d
Q
a
–Q
d
Description
HIGH/LOW
Common Select Input
Clock Pulse Input (Active Rising Edge)
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
Register Complementary Outputs (74F398)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
−1
mA/20 mA
−1
mA/20 mA
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2
74F398 • 74F399
Functional Description
The 74F398 and 74F399 are high-speed quad 2-port regis-
ters. They select four bits of data from either of two sources
(Ports) under control of a common Select input (S). The
selected data is transferred to a 4-bit output register syn-
chronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-type output register is fully edge-
triggered. The Data inputs (I
0x
, I
1x
) and Select input (S)
must be stable only a setup time prior to and hold time after
the LOW-to-HIGH transition of the Clock input for predict-
able operation. The 74F398 has both Q and Q outputs.
Function Table
Inputs
S
I
I
h
h
I
0
I
h
X
X
I
1
X
X
I
h
Q
L
H
L
H
Outputs
Q
(Note 1)
H
L
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
h
=
HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
I
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
X
=
Immaterial
Note 1:
74F398 only
Logic Diagram
*F398 Only
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F398 • 74F399
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage
(Min)—74F399
4000V
twice the rated I
OL
(mA)
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
I
CCH
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current (74F398)
Power Supply Current (74F398)
Power Supply Current (74F399)
Power Supply Current (74F399)
−60
25
25
22
22
4.75
3.75
−0.6
−150
38
38
34
34
5.0
7.0
50
µA
µA
µA
V
µA
mA
mA
mA
mA
mA
mA
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
Max
Max
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
0V
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH
V
O
=
LOW
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
Min
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
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4
74F398 • 74F399
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
Input Clock Frequency
Propagation Delay
CP to Q or Q
100
3.0
(Note 4)
3.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
140
5.7
6.8
7.5
9.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
100
3.0
3.0
8.5
ns
10.0
Max
MHz
Units
Note 4:
74F398 3.3 ns
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH or LOW
I
n
to CP
Hold Time, HIGH or LOW
I
n
to CP
Setup Time, HIGH or LOW
S to CP (F398)
Setup Time, HIGH or LOW
S to CP (F399)
Hold Time, HIGH or LOW
S to CP
CP Pulse Width
HIGH or LOW
3.0
3.0
1.0
1.0
7.5
7.5
7.5
7.5
0
0
4.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.0
1.0
1.0
8.5
8.5
8.5
8.5
0
0
4.0
5.0
ns
ns
ns
Max
Units
5
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