Philips Semiconductors
Product specification
16-bit latched transceivers with dual enable
(3-State)
74ABT16543
74ABTH16543
FEATURES
•
Two 8-bit octal transceivers with D-type latch
•
Live insertion/extraction permitted
•
Power-up 3-State
•
Power-up reset
•
Multiple V
CC
and GND pins minimize switching noise
•
Back-to-back registers for storage
•
Separate controls for data flow in each direction
•
74ABTH16543 incorporates bus-hold data inputs which eliminate
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
•
See 74ABT161543 for same function with Master Reset control
pins
and 200V per Machine Model
the need for external pull-up resistors to hold unused inputs
DESCRIPTION
The 74ABT16543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16543 16-bit registered transceiver contains two sets of
D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB, nLEBA) and Output
Enable (nOEAB, nOEBA) inputs are provided for each register to
permit independent control of data transfer in either direction. The
outputs are guaranteed to sink 64mA.
Two options are available, 74ABT16543 which does not have the
bus-hold feature and 74ABTH16543 which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
I
CCL
PARAMETER
Propagation delay
nAx to nBx
Input capacitance
I/O capacitance
Quiescent su ly current
supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC;
3-State
Outputs disabled; V
CC
= 5.5V
Outputs low; V
CC
= 5.5V
TYPICAL
2.5
2.2
3
7
550
9
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16543 DL
74ABT16543 DGG
74ABTH16543 DL
74ABTH16543 DGG
NORTH AMERICA
BT16543 DL
BT16543 DGG
BH16543 DL
BH16543 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1, 56
28, 29
3, 54
26, 31
2, 55
27, 30
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
1998 Feb 27
SYMBOL
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
1EAB, 1EBA,
2EAB, 2EBA
1LEAB, 1LEBA,
2LEAB, 2LEBA
GND
V
CC
2
NAME AND FUNCTION
Data inputs/outputs
Data inputs/outputs
A to B / B to A Output Enable inputs (active-Low)
A to B / B to A Enable inputs (active-Low)
A to B / B to A Latch Enable inputs (active-Low)
Ground (0V)
Positive supply voltage
853-1739 19026
Philips Semiconductors
Product specification
16-bit latched transceivers with dual enable
(3-State)
74ABT16543
74ABTH16543
LOGIC SYMBOL
FUNCTIONAL DESCRIPTION
The 74ABT16543 contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB) input and the A-to-B Latch
Enable (nLEAB) input are Low the A-to-B path is transparent.
5
6
8
9
10
12
13
14
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
3
54
2
55
1EAB
1EBA
1LEAB
1LEBA
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
1OEAB
1OEBA
1
56
A subsequent Low-to-High transition of the nLEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and nOEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA,
nLEBA, and nOEBA inputs.
52
51
49
48
47
45
44
43
15
16
17
19
20
21
23
24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
26
31
27
30
2EAB
2EBA
2LEAB
2LEBA
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
2OEAB
2OEBA
28
29
42
41
40
38
37
36
34
33
SH00038
FUNCTION TABLE
INPUTS
nOEXX
H
X
L
L
L
L
L
L
L
H =
h =
L =
l =
X =
↑
=
NC=
Z =
nEXX
X
H
↑
↑
L
L
L
L
L
nLEXX
X
X
L
L
↑
↑
L
L
H
nAx or nBx
X
X
h
l
h
l
H
L
X
OUTPUTS
nBx or nAx
Z
Z
Z
Z
H
L
H
L
NC
Disabled
Disabled
Disabled + Latch
Latch + Display
Transparent
Hold
STATUS
High voltage level
High voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
Low voltage level
Low voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
Don’t care
Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
No change
High impedance or “off” state
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit latched transceivers with dual enable
(3-State)
74ABT16543
74ABTH16543
LOGIC DIAGRAM
DETAIL A
D
LE
Q
nB0
nA0
Q
D
LE
nA1
nA2
nA3
nA4
nA5
nA6
nA7
DETAIL A X 7
nB1
nB2
nB3
nB4
nB5
nB6
nB7
nOEBA
nOEAB
nEBA
nEAB
nLEBA
nLEAB
SH00039
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
output in High state
Storage temperature range
–64
–65 to 150
mA
°C
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
UNIT
V
mA
V
mA
V
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Feb 27
5
PCB Design
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