v1.2
IGLOOe Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-
Power Flash*Freeze Mode
•
•
•
•
®
Pro (Professional) I/O
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2
V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
I/O Registers on Input, Output, and Enable Paths
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO
®
e Family
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
ARM Processor Support in IGLOOe FPGAs
• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available
with or without Debug
IGLOOe Product Family
IGLOOe Devices
ARM-Enabled IGLOOe Devices
System Gates
VersaTiles (D-flip-flops)
Quiescent Current (typical) in Flash*Freeze Mode (µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet
I/O Banks
Maximum User I/Os
Package Pins
FBGA
Globals
1
600 k
13,824
49
108
24
1k
Yes
6
18
8
270
FG256, FG484
AGLE600
AGLE3000
M1AGLE3000
3M
75,264
137
504
112
1k
Yes
6
18
8
620
FG484, FG896
Notes:
1. Refer to the
Cortex-M1 Handbook
for more information.
2. Six chip (main) and twelve quadrant global networks are available.
3. For devices supporting lower densities, refer to the
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
handbook.
October 2008
© 2008 Actel Corporation
I
I/Os Per Package
1
IGLOOe Devices
ARM-Enabled IGLOOe Devices
I/O Types
Package
FG256
FG484
FG896
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
IGLOOe Low-Power Flash
FPGAs with Flash*Freeze Technology
handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per
minibank (group of I/Os). When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular
I/O, the number of single-ended user I/Os available is reduced by one.
6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
7. "G" indicates RoHS-compliant packages. Refer to
"IGLOOe Ordering Information" on page III
for the location of the
"G" in the part number.
IGLOOe FPGAs Package Sizes Dimensions
Package
Length × Width (mm × mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
FG256
17 × 17
289
1
1.6
FG484
23 × 23
529
1
2.23
FG896
31 × 31
961
1
2.23
Single-Ended
I/O
1
165
270
–
Differential
I/O Pairs
79
135
–
Single-Ended
I/O
1
–
341
620
Differential
I/O Pairs
–
168
310
AGLE600
AGLE3000
M1AGLE3000
II
v1.2
IGLOOe Low-Power Flash FPGAs
IGLOOe Ordering Information
AGLE3000
V2
_
FG
G
896
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant Packaging
Package Type
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOOe Devices
AGLE600 = 600,000 System Gates
AGLE3000 = 3,000,000 System Gates
IGLOOe Devices with Cortex-M1
M1AGLE3000 = 3,000,000 System Gates
Notes:
1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics
provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be
added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
v1.2
III
Temperature Grade Offerings
AGLE600
Package
FG256
FG484
FG896
C, I
C, I
–
AGLE3000
M1AGLPE3000
–
C, I
C, I
Note:
C = Commercial temperature range: 0°C to 70°C ambient temperature.
I = Industrial temperature range: –40°C to 85°C ambient temperature.
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
–F
1
Std.
✓
–
✓
✓
IV
v1.2
1 – IGLOOe Device Family Overview
General Description
The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA,
a single-chip solution, small footprint packages, reprogrammability, and an abundance of
advanced features.
The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low-
power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power
management through I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the
IGLOOe device is completely functional in the system. This allows the IGLOOe device to control
system power management based on external inputs (e.g., scanning for keyboard stimulus) while
consuming minimal power.
Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power,
single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have
up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620
user I/Os.
M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM
for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA
fabric. It has a three-stage pipeline that offers a good balance between low-power consumption
and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M
instruction set, has a configurable nested interrupt controller, and can be implemented with or
without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not
support AES decryption.
Flash*Freeze Technology
The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn
off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction
in power consumption, thus achieving the lowest total system power.
When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and
data is retained.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe
devices the best fit for portable electronics.
v1.2
1-1
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