AGLE3000V5-FG896ES datasheet, PDF

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AGLE3000V5-FG896ES: DescriptionFPGA, 3000000 GATES, 250 MHz, PBGA896; Categorysemiconductor Programmable logic devices; File Size5MB，156 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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AGLE3000V5-FG896ES Overview

FPGA, 3000000 GATES, 250 MHz, PBGA896

AGLE3000V5-FG896ES Parametric

Parameter Name	Attribute value
Number of terminals	896
Minimum operating temperature	-40 Cel
Maximum operating temperature	85 Cel
Processing package description	31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-896
each_compli	Yes
EU RoHS regulations	Yes
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	250 MHz
jesd_30_code	S-PBGA-B896
jesd_609_code	e1
moisture_sensitivity_level	3
Number of equivalent gate circuits	3.00E6
organize	3000000 GATES
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
packaging shape	SQUARE
Package Size	GRID ARRAY
eak_reflow_temperature__cel_	250
qualification_status	COMMERCIAL
seated_height_max	2.44 mm
Rated supply voltage	1.2 V
Minimum supply voltage	1.14 V
Maximum supply voltage	1.58 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	INDUSTRIAL
terminal coating	TIN SILVER COPPER
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
ime_peak_reflow_temperature_max__s_	40
length	31 mm
width	31 mm

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v1.2

IGLOOe Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-

Power Flash*Freeze Mode

•

Pro (Professional) I/O

•

700 Mbps DDR, LVDS-Capable I/Os

1.2

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

I/O Registers on Input, Output, and Enable Paths

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/-Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the IGLOO

e Family

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

ARM Processor Support in IGLOOe FPGAs

• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available

with or without Debug

IGLOOe Product Family

IGLOOe Devices

ARM-Enabled IGLOOe Devices

System Gates

VersaTiles (D-flip-flops)

Quiescent Current (typical) in Flash*Freeze Mode (µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

CCCs with Integrated PLLs

VersaNet

I/O Banks

Maximum User I/Os

Package Pins

FBGA

Globals

600 k

13,824

108

Yes

270

FG256, FG484

AGLE600

AGLE3000

M1AGLE3000

75,264

137

504

112

Yes

620

FG484, FG896

Notes:

1. Refer to the

Cortex-M1 Handbook

for more information.

2. Six chip (main) and twelve quadrant global networks are available.

3. For devices supporting lower densities, refer to the

IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology

handbook.

October 2008

1 – IGLOOe Device Family Overview

General Description

The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA,

a single-chip solution, small footprint packages, reprogrammability, and an abundance of

advanced features.

The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low-

power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power

management through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the

IGLOOe device is completely functional in the system. This allows the IGLOOe device to control

system power management based on external inputs (e.g., scanning for keyboard stimulus) while

consuming minimal power.

Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have

up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620

user I/Os.

M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M

instruction set, has a configurable nested interrupt controller, and can be implemented with or

without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not

support AES decryption.

Flash*Freeze Technology

The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn

off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe

devices the best fit for portable electronics.

v1.2

1-1

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