Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
FEATURES
•
3-state inverting outputs for bus
oriented applications
•
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor
•
Common 3-state output enable
input
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “563” is functionally identical to
the “573”, but has inverted outputs.
The “563” consists of eight D-type
transparent latches with 3-state
inverting outputs. The LE and OE are
74HC/HCT563
common to all latches.
When LE is HIGH, data at the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
for HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay D
n
, LE to Q
n
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
3.5
19
HCT
16
3.5
19
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
FUNCTION TABLE
INPUTS
OPERATING
MODES
OE LE
enable and
read register
latch and read
register
latch register
and disable
outputs
Notes
L
L
L
L
H
H
H
H
L
L
L
L
D
n
L
H
l
h
l
h
74HC/HCT563
INTER-
NAL
LATCHES
L
H
L
H
L
H
OUT-
PUTS
Q
0
to Q
7
H
L
H
L
Z
Z
Fig.4 Functional diagram.
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
Z = high impedance OFF-state
Fig.5 Logic diagram.
December 1990
4
NXP MCU
京公网安备 11010802033920号
EEWORLD
