INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7597
8-bit shift register with input latches
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit shift register with input latches
FEATURES
•
8-bit parallel input latches
•
Shift register has direct overriding load and clear
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7597 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
74HC/HCT7597
The 74HC/HCT7597 both consist of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift register.
When LE is LOW, data at the D
n
inputs enter the latches.
In this condition the latches are transparent, i.e. a latch
output will change state each time its corresponding
D-input changes.
When LE is HIGH the latches store the information that
was present at the D-inputs, a set-up time preceding the
LOW-to-HIGH transition of LE.
The shift register has a positive edge-triggered clock,
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
SH
CP
to Q
LE to Q
PL to Q
D
7
to Q
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF; V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency SH
CP
input capacitance
power dissipation capacitance per package
notes 1, 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
22
20
20
99
3.5
29
17
27
23
24
79
3.5
30
ns
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input latches
PIN DESCRIPTION
PIN NO.
8
9
10
11
12
13
14
15, 1, 2, 3, 4, 5, 6, 7
16
SYMBOL
GND
Q
MR
SH
CP
LE
PL
D
S
D
0
to D
7
V
CC
NAME AND FUNCTION
ground (0 V)
serial data output
74HC/HCT7597
asynchronous reset input (active LOW)
shift clock input (LOW-to-HIGH, edge-triggered)
latch enable input (active LOW)
parallel load input (active LOW)
serial data input
parallel data inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit shift register with input latches
FUNCTION TABLE
LE
L
H
X
X
X
X
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH CP transition
SH
CP
X
X
X
X
X
↑
PL
X
X
L
L
H
H
MR
X
X
H
L
L
H
FUNCTION
data enabled to input latches (transparent)
data stored into latches (non-transparent)
data transferred from input latches to shift register
74HC/HCT7597
invalid logic, state of shift register indeterminate when signals removed
shift register cleared
shift register clocked Q
n
= Q
n-1
, Q
0
= D
S
Fig.4 Functional diagram.
December 1990
4
Embedded System
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