V 5%, V
AD7837/AD7847–SPECIFICATIONS
1
(V = +15specifications T= –15 TV
= O V. V = V = +10 V, R = 2 k , C = 100 pF [V connected to R AD7837]. All
to
DD
SS
REFA
REFB
L
L
OUT
FB
MIN
5%, AGNDA = AGNDB = DGND
MAX
unless otherwise noted.)
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
2
Differential Nonlinearity
2
Zero Code Offset Error
2
@ +25°C
T
MIN
to T
MAX
Gain Error
2
@ +25°C
T
MIN
to T
MAX
REFERENCE INPUTS
V
REF
Input Resistance
V
REFA
, V
REFB
Resistance Matching
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
Input Capacitance
3
ANALOG OUTPUTS
DC Output Impedance
Short Circuit Current
POWER REQUIREMENTS
4
V
DD
Range
V
SS
Range
Power Supply Rejection
∆Gain/∆V
DD
∆Gain/∆V
SS
I
DD
I
SS
AC CHARACTERISTICS
2, 3
Voltage Output Settling Time
A Version
B Version
S Version
Units
Test Conditions/Comments
12
±
1
±
1
±
2
±
4
±
4
±
5
12
±
1/2
±
1
±
2
±
3
±
2
±
3
12
±
1
±
1
±
2
±
4
±
4
±
5
Bits
LSB max
LSB max
mV max
mV max
LSB max
LSB max
Guaranteed Monotonic
DAC Latch Loaded with All 0s
Temperature Coefficient =
±
5
µV/°C
typ
DAC Latch Loaded with All 1s
Temperature Coefficient =
±
2 ppm of
FSR/°C typ
8/13
±
2
2.4
0.8
±
1
8
8/13
±
2
2.4
0.8
±
1
8
8/13
±
2
2.4
0.8
±
1
8
kΩ min/max
% max
Typical Input Resistance = 10 kΩ
Typically
±
0.25%
V min
V max
µA
max
pF max
Ω
typ
mA typ
Digital Inputs at 0 V and V
DD
0.2
11
0.2
11
0.2
11
V
OUT
Connected to AGND
14.25/15.75
–14.25/–15.75
±
0.01
±
0.01
8
6
14.25/15.75
14.25/15.75
–14.25/–15.75 –14.25/–15.75
±
0.01
±
0.01
8
6
±
0.01
±
0.01
8
6
V min/max
V min/max
% per % max
% per % max
mA max
mA max
V
DD
= 15 V
±
5%, V
REF
= –10 V
V
SS
= –15 V
±
5%, V
REF
= +10 V
Outputs Unloaded. Inputs at Thresholds.
Typically 5 mA
Outputs Unloaded. Inputs at Thresholds.
Typically 3 mA
Settling Time to Within
±
1/2 LSB of Final
Value. DAC Latch Alternately Loaded
with All 0s and All 1s
1 LSB Change Around Major Carry
V
REFA
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REFB
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REF
= 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
V
REF
= 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
V
REF
= 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
V
REF
= 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
Code Transition from All 0s to All 1s and
Vice Versa
See Typical Performance Graphs
Amplifier Noise and Johnson Noise of R
FB
3
5
11
10
–95
–95
–90
750
175
–88
1
3
5
11
10
–95
–95
–90
750
175
–88
1
3
5
11
10
–95
–95
–90
750
175
–88
1
µs
typ
µs
max
V/µs typ
nV secs typ
dB typ
dB typ
dB typ
kHz typ
kHz typ
dB typ
nV secs typ
Slew Rate
Digital-to-Analog Glitch Impulse
Channel-to-Channel Isolation
V
REFA
to V
OUTB
V
REFB
to V
OUTA
Multiplying Feedthrough Error
Unity Gain Small Signal BW
Full Power BW
Total Harmonic Distortion
Digital Crosstalk
Output Noise Voltage @ +25°C
(0.1 Hz to 10 Hz)
Digital Feedthrough
2
1
2
1
2
1
µV
rms typ
nV secs typ
NOTES
1
Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
The Devices are functional with V
DD
/V
SS
=
±
12 V (See typical performance graphs.).
Specifications subject to change without notice.
–2–
REV. C
AD7837/AD7847
TIMING CHARACTERISTICS
1, 2, 3
Parameter
t
1
t
2
t
3
t
4
t
5
t
6 4
t
7 4
t
8 4
0
0
30
80
0
0
0
50
(V
DD
= +15 V
5%, V
SS
= –15 V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
5%, AGNDA = AGNDB = DGND = O V)
Conditions/Comments
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulsewidth
Data Valid to
WR
Setup Time
Data Valid to
WR
Hold Time
Address to
WR
Setup Time
Address to
WR
Hold Time
LDAC
Pulsewidth
Limit at T
MIN
, T
MAX
(All Versions)
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 3 and 5.
3
Guaranteed by design and characterization, not production tested.
4
AD7837 only.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
ORDERING GUIDE
V
DD
to DGND, AGNDA, AGNDB . . . . . . . –0.3 V to +17 V
V
SS1
to DGND, AGNDA, AGNDB . . . . . . . +0.3 V to –17 V
V
REFA
, V
REFB
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
AGNDA, AGNDB to DGND . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUTA2
, V
OUTB2
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
R
FBA3
, R
FBB3
to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial/Industrial (A, B Versions) . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
If V
SS
is open circuited with V
DD
and either AGND applied, the V
SS
pin will float
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode connected between V
SS
and AGND (cathode to AGND) ensures
the Maximum Ratings will be observed.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
3
AD7837 only.
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
Model
1
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Relative
Accuracy
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
Package
Option
2
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
AD7837AN
AD7837BN
AD7837AR
AD7837BR
AD7837AQ
AD7837BQ
AD7837SQ
AD7847AN
AD7847BN
AD7847AR
AD7847BR
AD7847AQ
AD7847BQ
AD7847SQ
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
2
N = Plastic DIP; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD7837/AD7847
TERMINOLOGY
Relative Accuracy (Linearity)
Channel-to-Channel Isolation
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints. It is measured after
allowing for zero and full-scale errors and is expressed in LSBs
or as a percentage of full-scale reading.
Differential Nonlinearity
This is an ac error due to capacitive feedthrough from the V
REF
input on one DAC to V
OUT
on the other DAC. It is measured
with the DAC latches loaded with all 0s.
Digital Feedthrough
Digital feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the data inputs change state,
but the data in the DAC latches is not changed.
For the AD7837, it is measured with
LDAC
held high. For the
AD7847, it is measured with
CSA
and
CSB
held high.
Digital Crosstalk
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB or less
over the operating temperature range ensures monotonicity.
Zero Code Offset Error
Zero code offset error is the error in output voltage from V
OUTA
or V
OUTB
with all 0s loaded into the DAC latches. It is due to a
combination of the DAC leakage current and offset errors in the
output amplifier.
Gain Error
Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in digital code on the DAC
latch of the other converter. It is specified in nV secs.
Digital-to-Analog Glitch Impulse
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded. It does
not include offset error.
Total Harmonic Distortion
This is the voltage spike that appears at the output of the DAC
when the digital code changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs and is
measured for a 1 LSB change around the major carry transition
(0111 1111 1111 to 1000 0000 0000 and vice versa).
Unity Gain Small Signal Bandwidth
This is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.
Multiplying Feedthrough Error
This is the frequency at which the small signal voltage output
from the output amplifier is 3 dB below its dc level. It is mea-
sured with the DAC latch loaded with all 1s.
Full Power Bandwidth
This is an ac error due to capacitive feedthrough from the V
REF
input to V
OUT
of the same DAC when the DAC latch is loaded
with all 0s.
This is the maximum frequency for which a sinusoidal input
signal will produce full output at rated load with a distortion
less than 3%. It is measured with the DAC latch loaded with
all 1s.
AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17–20
21–24
Mnemonic
CS
R
FBA
V
REFA
V
OUTA
AGNDA
V
DD
V
SS
AGNDB
V
OUTB
V
REFB
DGND
R
FBB
WR
LDAC
A1
A0
DB7–DB4
DB3–DB0
Description
Chip Select. Active low logic input. The device is selected when this input is active.
Amplifier Feedback Resistor for DAC A.
Reference Input Voltage for DAC A. This may be an ac or dc signal.
Analog Output Voltage from DAC A.
Analog Ground for DAC A.
Positive Power Supply.
Negative Power Supply.
Analog Ground for DAC B.
Analog Output Voltage from DAC B.
Reference Input Voltage for DAC B. This may be an ac or dc signal.
Digital Ground. Ground reference for digital circuitry.
Amplifier Feedback Resistor for DAC B.
Write Input.
WR
is an active low logic input which is used in conjunction with
CS,
A0 and A1 to
write data to the input latches.
DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when
LDAC
is taken low.
Address Input. Most significant address input for input latches (see Table II).
Address Input. Least significant address input for input latches (see Table II).
Data Bit 7 to Data Bit 4.
Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8.
–4–
REV. C
AD7837/AD7847
AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
Pin
11
12
13
14
15
16
17
18
19
10
11
12
13
14–24
Mnemonic
CSA
CSB
V
REFA
V
OUTA
AGNDA
V
DD
V
SS
AGNDB
V
OUTB
V
REFB
DGND
DB11
WR
DB10–DB0
Description
Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low.
Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low.
Reference Input Voltage for DAC A. This may be an ac or dc signal.
Analog Output Voltage from DAC A.
Analog Ground for DAC A.
Positive Power Supply.
Negative Power Supply.
Analog Ground for DAC B.
Analog Output Voltage from DAC B.
Reference Input Voltage for DAC B. This may be an ac or dc signal.
Digital Ground.
Data Bit 11 (MSB).
Write Input.
WR
is a positive edge triggered input which is used in conjunction with
CSA
and
CSB
to write data to the DAC latches.
Data Bit 10 to Data Bit 0 (LSB).
AD7837 PIN CONFIGURATION
DIP AND SOIC
AD7847 PIN CONFIGURATION
DIP AND SOIC
CS
R
FBA
V
REFA
V
OUTA
AGNDA
V
DD
V
SS
AGNDB
V
OUTB
1
2
3
4
5
6
24
DB0
23
DB1
22
DB2
21
DB3
CSA
CSB
V
REFA
V
OUTA
AGNDA
V
DD
V
SS
AGNDB
V
OUTB
1
2
3
4
5
6
24
DB0
23
DB1
22
DB2
21
DB3
AD7837
20
DB4
AD7847
20
DB4
TOP VIEW
19
DB5
(Not to Scale)
18
DB6
7
8
9
17
DB7
16
A0
15
A1
14
LDAC
13
WR
TOP VIEW
19
DB5
(Not to Scale)
18
DB6
7
8
9
17
DB7
16
DB8
15
DB9
14
DB10
13
WR
V
REFB 10
DGND
11
R
FBB 12
V
REFB 10
DGND
11
DB11
12
REV. C
–5–
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