Advance Information
MPC8272EC
Rev. 0.1 9/2003
MPC8272 Family
Hardware Specifications
This hardware specification contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the MPC8272 family of
devices—the MPC8272, the MPC8248, the MPC8271, and the MPC8247. The CPU on these
devices is a 32-bit PowerPC
TM
core that incorporates memory management units (MMUs)
and instruction and data caches and that implements the PowerPC instruction set. These
devices are .13µm (HiP7) members of the PowerQUICC II™ family of integrated
communications processors. They include a modified communications processor module
(CPM) and an integrated security engine (SEC) for encryption (the MPC8272 and the
MPC8248 only).
All four devices are collectively referred to throughout this hardware specification as ‘the
MPC8272’ unless otherwise noted. The following topics are addressed:
Topic
Section 1, “Features”
Section 2, “Electrical and Thermal Characteristics”
Section 2.1, “DC Electrical Characteristics”
Section 2.2, “Thermal Characteristics”
Section 2.3, “AC Electrical Characteristics”
Section 3, “Clock Configuration Modes”
Section 4, “Pinout”
Section 5, “Package”
Section 6, “Ordering Information”
Section 7, “Document Revision History”
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2
6
6
10
11
18
34
45
48
48
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Figure 1 shows the superset block diagram.
16 Kbytes
I-Cache
I-MMU
G2_LE Core
System Interface Unit
(SIU)
16 Kbytes
D-Cache
D-MMU
Bus Interface Unit
60x-to-PCI
Bridge
Memory Controller
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
4 KB
Interrupt
Instruction
Controller
RAM
16 KB
Data
RAM
Clock Counter
Serial
DMA
Virtual
IDMAs
System Functions
PCI Bus
32 bits, up to 66 MHz
Security (SEC)
1
60x Bus
32-bit RISC Microcontroller
and Program ROM
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
USB 2.0
Time Slot Assigner
Serial interface
Serial Interface
2 TDM Ports
2 MII/RMII
Ports
1 8-bit Utopia
Port
2
Non-Multiplexed
I/O
Note
1
MPC8272/8248 only
2
MPC8272/8271 only
Figure 1. Block Diagram
1
•
Features
Dual-issue integer (G2_LE) core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting frequencies of 266-400 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
— Floating-point unit (FPU) supports floating-point arithmetic
— Support for cache locking
The major features of the MPC8272 are as follows:
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MPC8272 Family Hardware Specifications
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MOTOROLA
Features
•
•
•
•
•
•
•
•
•
•
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
Separate PLLs for G2_LE core and for the communications processor module (CPM)
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1,
7:1, and 8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs—up to two external masters
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Eight bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x)
— Dedicated interface logic for SDRAM
Disable CPU mode
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
MOTOROLA
MPC8272 Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
•
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.)
Universal serial bus (USB) controller
— Supports USB 2.0 full/low rate compatible
— USB host mode
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
— Supports USB slave mode
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Two fast communication controllers (FCCs) supporting the following protocols:
– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—up to T3 rates (clear channel)
– One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155
Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0
CBR, VBR, UBR, ABR traffic types, up to 64-K external connections
— Three serial communications controllers (SCCs) identical to those on the MPC860 supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BiSync) communications
– Transparent
– QUICC multichannel controller (QMC) up to 64 channels
• Independent transmit and receive routing, frame synchronization.
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MPC8272 Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
•
• Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM
highways
• Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN
basic rate, ISDN primary rate, and user defined.
• Subchanneling on each time slot.
• Independent transmit and receive routing, frame synchronization and clocking
• Concatenation of any not necessarily consecutive time slots to channels independently
for Rx/Tx
• Supports H1,H11, and H12 channels
• Allows dynamic allocation of channels
– SCC3 in NMSI mode is not usable when USB is enabled.
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provides management for BRI devices as general-circuit interface (GCI) controllers in
time-division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One I
2
C controller (identical to the MPC860 I
2
C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to two TDM interfaces
– Supports one group of two TDM channels
– 1024 bytes of SI RAM
— Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,
SCC, SMC, and USB serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
— PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI host bridge or peripheral capabilities
— Includes four DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes the configuration registers required by the PCI standard (which are automatically
loaded from the EPROM to configure the MPC8272) and message and doorbell registers
— Supports the I
2
O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August
3, 1998)
— Support for 66-MHz, 3.3-V specification
MOTOROLA
MPC8272 Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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