Philips Semiconductors
Product specification
Voltage regulator diodes
FEATURES
•
Glass passivated
•
High maximum operating
temperature
•
Low leakage current
•
Excellent stability
•
Zener working voltage range:
7.5 to 270 V for 38 types
•
Transient suppressor stand-off
voltage range:
6.2 to 430 V for 45 types
•
Available in ammo-pack.
DESCRIPTION
Rugged glass SOD57 package, using
a high temperature alloyed
BZT03 series
construction. This package is
hermetically sealed and fatigue free
as coefficients of expansion of all
used parts are matched.
2/3 page
k
(Datasheet)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
P
tot
PARAMETER
total power dissipation
a
MAM204
Fig.1 Simplified outline (SOD57) and symbol.
CONDITIONS
T
tp
= 25
°C;
lead length 10 mm; see Fig.2
T
amb
= 45
°C;
see Fig.2;
PCB mounted (see Fig.6)
MIN.
−
−
−
MAX.
3.25
1.30
10
600
300
+175
+175
UNIT
W
W
W
W
W
°C
°C
P
ZRM
P
ZSM
P
RSM
T
stg
T
j
repetitive peak reverse power
dissipation
non-repetitive peak reverse
power dissipation
non-repetitive peak reverse
power dissipation
storage temperature
junction temperature
t
p
= 100
µs;
square pulse;
T
j
= 25
°C
prior to surge; see Fig.3
10/1000
µs
exponential pulse (see Fig.4);
T
j
= 25
°C
prior to surge
−
−
−65
−65
1996 Jun 11
2
Philips Semiconductors
Product specification
Voltage regulator diodes
ELECTRICAL CHARACTERISTICS
Total series
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
F
PARAMETER
forward voltage
CONDITIONS
I
F
= 0.5 A; see Fig.5
BZT03 series
MAX.
1.2
V
UNIT
Per type when used as voltage regulator diodes
T
j
= 25
°C
unless otherwise specified.
TYPE
No.
SUFFIX
(1)
WORKING VOLTAGE
V
Z
(V) at I
Z
MIN.
NOM.
7.5
8.2
9.1
10
11
12
13
15
16
18
20
22
24
27
30
33
36
39
43
47
51
56
62
68
75
82
91
MAX.
7.9
8.7
9.6
10.6
11.6
12.7
14.1
15.6
17.1
19.1
21.2
23.3
25.6
28.9
32
35
38
41
46
50
54
60
66
72
79
87
96
DIFFERENTIAL TEMPERATURE
TEST
RESISTANCE
COEFFICIENT CURRENT
r
dif
(Ω) at I
Z
TYP.
1
1
2
2
4
4
5
5
6
6
6
6
7
7
8
8
21
21
24
24
25
25
25
25
30
30
60
MAX.
2
2
4
4
7
7
10
10
15
15
15
15
15
15
15
15
40
40
45
45
60
60
80
80
100
100
200
S
Z
(%/K) at I
Z
MIN.
0.00
0.03
0.03
0.05
0.05
0.05
0.05
0.05
0.06
0.06
0.06
0.06
0.06
0.06
0.06
0.06
0.06
0.06
0.07
0.07
0.07
0.07
0.08
0.08
0.08
0.08
0.09
MAX.
0.07
0.08
0.08
0.09
0.10
0.10
0.10
0.10
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.12
0.12
0.12
0.12
0.13
0.13
0.13
0.13
0.13
I
Z
(mA)
100
100
50
50
50
50
50
50
25
25
25
25
25
25
25
25
10
10
10
10
10
10
10
10
10
10
5
REVERSE CURRENT
at REVERSE VOLTAGE
I
R
(µA)
MAX.
750
600
20
10
4
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
R
(V)
5.6
6.2
6.8
7.5
8.2
9.1
10
11
12
13
15
16
18
20
22
24
27
30
33
36
39
43
47
51
56
62
68
C7V5
C8V2
C9V1
C10
C11
C12
C13
C15
C16
C18
C20
C22
C24
C27
C30
C33
C36
C39
C43
C47
C51
C56
C62
C68
C75
C82
C91
7.0
7.7
8.5
9.4
10.4
11.4
12.4
13.8
15.3
16.8
18.8
20.8
22.8
25.1
28
31
34
37
40
44
48
52
58
64
70
77
85
1996 Jun 11
3
FPGA/CPLD
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