SSTUM32865ET/G datasheet, PDF - EEWORLD Datasheet

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SSTUM32865ET/G: DescriptionIC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160, FF/Latch; Categorylogic logic; File Size141KB，28 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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SSTUM32865ET/G Overview

IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160, FF/Latch

SSTUM32865ET/G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	BGA
package instruction	9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
Contacts	160
Manufacturer packaging code	SOT-802-2
Reach Compliance Code	unknown
series	SSTU
JESD-30 code	R-PBGA-B160
length	13 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	2
Number of digits	28
Number of functions	1
Number of terminals	160
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	OPEN-DRAIN
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA160,12X18,25
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
propagation delay (tpd)	1.4 ns
Certification status	Not Qualified
Maximum seat height	1.15 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
Trigger type	POSITIVE EDGE
width	9 mm
minfmax	450 MHz

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SSTUM32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800

RDIMM applications

Rev. 01 — 19 September 2007

Product data sheet

1. General description

The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R

4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUM32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it is permanently

conﬁgured for high output drive strength. This allows use in high density designs with

heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two

additional chip select inputs, which allow more versatile enabling and disabling in densely

populated memory modules. Both added features (drive strength and chip selects) are

fully backward compatible to the JEDEC standard register.

The SSTUM32865 is packaged in a 160-ball, 12

18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm

13 mm of board space, allows for adequate signal routing and escape using

conventional card technology.

2. Features

28-bit data register supporting DDR2

Fully compliant to JEDEC standard for SSTUB32865

Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2

SSTUB32864 or 2

SSTUB32866)

Parity checking function across 22 input data bits

Parity out signal

Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

Meets or exceeds SSTUB32865 JEDEC standard speed performance

Supports up to 450 MHz clock frequency of operation

Permanently conﬁgured for high output drive

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing state

Two additional chip select inputs allow optional ﬂexible enabling and disabling

SSTUM32865ET/G Related Products

	SSTUM32865ET/G	SSTUM32865ET/S
Description	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160, FF/Latch	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160, FF/Latch
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	BGA	BGA
package instruction	9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160	9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
Contacts	160	160
Manufacturer packaging code	SOT-802-2	SOT-802-2
Reach Compliance Code	unknown	unknown
series	SSTU	SSTU
JESD-30 code	R-PBGA-B160	R-PBGA-B160
length	13 mm	13 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Humidity sensitivity level	2	2
Number of digits	28	28
Number of functions	1	1
Number of terminals	160	160
Maximum operating temperature	70 °C	85 °C
Output characteristics	OPEN-DRAIN	OPEN-DRAIN
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA
Encapsulate equivalent code	BGA160,12X18,25	BGA160,12X18,25
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	1.8 V	1.8 V
propagation delay (tpd)	1.4 ns	1.4 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.15 mm	1.15 mm
Maximum supply voltage (Vsup)	2 V	2 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
Temperature level	COMMERCIAL	OTHER
Terminal form	BALL	BALL
Terminal pitch	0.65 mm	0.65 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	9 mm	9 mm
minfmax	450 MHz	450 MHz

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