Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
•
Wide supply voltage range from 2.0 to 6.0 V
•
Symmetrical output impedance
•
High noise immunity
•
Low power dissipation
•
Balanced propagation delays
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
74HC74; 74HCT74
GENERAL DESCRIPTION
The 74HC/HCT74 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary
Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC74 the condition is V
I
= GND to V
CC
.
For 74HCT74 the condition is V
I
= GND to V
CC
−
1.5 V.
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
15
16
76
3.5
24
15
18
18
59
3.5
29
ns
ns
ns
MHz
pF
pF
HCT
UNIT
2003 Jul 10
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
positive supply voltage
DESCRIPTION
asynchronous reset-direct input (active LOW)
74HC74; 74HCT74
handbook, halfpage
handbook, halfpage
1RD
1
VCC
14
13
12
2RD
2D
2CP
2SD
2Q
1RD
1D
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
MNA417
14 VCC
13 2RD
12 2D
1D
1CP
1SD
1Q
2
3
4
5
6
7
Top view
GND
8
2Q
74
11 2CP
10 2SD
GND
(1)
11
10
9
9
2Q
1Q
8 2Q
MNB038
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP14, SO14 and
(T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
2003 Jul 10
4
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