MPC564MZP56R2 datasheet, PDF - EEWORLD Datasheet

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MPC564MZP56R2: DescriptionRISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388; CategoryThe embedded processor and controller Microcontrollers and processors; File Size10MB，1420 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MPC564MZP56R2 Overview

RISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388

MPC564MZP56R2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	BGA, BGA388,26X26,40
Reach Compliance Code	unknown
Has ADC	NO
Address bus width	24
bit size	32
maximum clock frequency	20 MHz
DAC channel	NO
DMA channel	NO
External data bus width	32
JESD-30 code	S-PBGA-B388
length	27 mm
Number of I/O lines	16
Number of terminals	388
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
ROM programmability	FLASH
Maximum seat height	2.55 mm
speed	56 MHz
Maximum supply voltage	2.7 V
Minimum supply voltage	2.5 V
Nominal supply voltage	2.6 V
surface mount	YES
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	27 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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MPC561/MPC563 Reference Manual

Additional Devices Supported:

MPC562

MPC564

MPC561RM

REV 1.2

08/2005

Contents

Paragraph

Number

Title

About This Book lxxvii

Audience ..................................................................................................................... lxxvii

Organization ................................................................................................................ lxxvii

Suggested Reading ........................................................................................................ lxxx

Conventions and Nomenclature .................................................................................... lxxx

Notational Conventions ............................................................................................... lxxxi

Acronyms and Abbreviations ..................................................................................... lxxxii

References .................................................................................................................. lxxxiii

Page

Number

Chapter 1

Overview

1.1

1.2

1.3

1.3.1

1.3.1.1

1.3.1.2

1.3.1.3

1.3.1.4

1.3.1.5

1.3.1.6

1.3.1.7

1.3.1.8

1.3.2

1.3.3

1.3.3.1

1.3.3.2

1.3.3.3

1.3.3.4

1.3.3.5

1.3.3.6

1.4

1.5

1.6

1.7

1.8

Introduction ..................................................................................................................... 1-1

Block Diagram ................................................................................................................ 1-2

Key Features ................................................................................................................... 1-3

High-Performance CPU System ................................................................................. 1-3

RISC MCU Central Processing Unit (RCPU) ........................................................ 1-4

Unified System Interface Unit (USIU) ................................................................... 1-4

Burst Buffer Controller (BBC) Module .................................................................. 1-4

Flexible Memory Protection Unit ........................................................................... 1-5

Memory Controller ................................................................................................. 1-5

512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –

MPC563/MPC564 Only 1-5

32-Kbyte Static RAM (CALRAM) ........................................................................ 1-6

General Purpose I/O Support (GPIO) ..................................................................... 1-6

Nexus Debug Port (Class 3) ........................................................................................ 1-6

Integrated I/O System ................................................................................................. 1-6

Two Time Processor Units (TPU3) ........................................................................ 1-6

22-Channel Modular I/O System (MIOS14) .......................................................... 1-6

Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ........ 1-7

Three CAN 2.0B Controller (TouCAN) Modules .................................................. 1-7

Queued Serial Multi-Channel Module (QSMCM) ................................................. 1-8

Peripheral Pin Multiplexing (PPM) ........................................................................ 1-8

MPC561/MPC563 Optional Features ............................................................................. 1-9

Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9

Additional MPC561/MPC563 Differences ................................................................... 1-10

SRAM Keep-Alive Power Behavior ............................................................................. 1-11

MPC561/MPC563 Address Map .................................................................................. 1-11

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor

iii

Contents

Paragraph

Number

1.9

Title

Page

Number

Supporting Documentation List .................................................................................... 1-14

Chapter 2

Signal Descriptions

2.1

2.2

2.2.1

2.2.2

2.3

2.4

2.5

2.5.1

2.5.2

2.5.3

2.6

2.6.1

2.6.2

2.6.3

2.6.4

2.6.4.1

2.6.4.2

2.6.4.3

2.6.4.4

2.6.5

Signal Groupings ............................................................................................................ 2-1

Signal Summary .............................................................................................................. 2-3

MPC561/MPC563 Signal Multiplexing ................................................................... 2-20

READI Port Signal Sharing ...................................................................................... 2-21

Pad Module Configuration Register (PDMCR) ............................................................ 2-22

Pad Module Configuration Register (PDMCR2) .......................................................... 2-23

MPC561/MPC563 Development Support Signal Sharing ............................................ 2-28

JTAG Mode Selection .............................................................................................. 2-29

BDM Mode Selection ............................................................................................... 2-30

Nexus Mode Selection .............................................................................................. 2-30

Reset State ..................................................................................................................... 2-31

Signal Functionality Configuration Out of Reset ..................................................... 2-31

Signal State During Reset ......................................................................................... 2-31

Power-On Reset and Hard Reset .............................................................................. 2-32

Pull-Up/Pull-Down ................................................................................................... 2-32

Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-32

Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-32

Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-32

Pull Device Select (PULL_SEL) .......................................................................... 2-33

Signal Reset States .................................................................................................... 2-33

Chapter 3

Central Processing Unit

3.1

3.2

3.3

3.4

3.4.1

3.4.2

3.4.3

3.4.4

3.5

3.6

RCPU Block Diagram .................................................................................................... 3-1

RCPU Key Features ........................................................................................................ 3-3

Instruction Sequencer ..................................................................................................... 3-3

Independent Execution Units .......................................................................................... 3-4

Branch Processing Unit (BPU) ................................................................................... 3-5

Integer Unit (IU) ......................................................................................................... 3-5

Load/Store Unit (LSU) ............................................................................................... 3-6

Floating-Point Unit (FPU) .......................................................................................... 3-6

Levels of the PowerPC ISA Architecture ....................................................................... 3-6

RCPU Programming Model ............................................................................................ 3-7

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor

Contents

Paragraph

Number

3.7

3.7.1

3.7.2

3.7.3

3.7.4

3.7.4.1

3.7.4.2

3.7.4.3

3.7.5

3.7.6

3.7.7

3.8

3.9

3.9.1

3.9.2

3.9.3

3.9.4

3.9.5

3.9.6

3.9.7

3.9.8

3.9.9

3.9.10

3.9.10.1

3.9.10.2

3.9.10.3

3.10

3.10.1

3.10.2

3.10.3

3.11

3.11.1

3.11.2

3.11.3

3.11.4

3.11.5

3.12

3.13

3.13.1

3.13.2

Title

Page

Number

User Instruction Set Architecture (UISA)

Register Set ............................................................................................................... 3-12

General-Purpose Registers (GPRs) ........................................................................... 3-12

Floating-Point Registers (FPRs) ............................................................................... 3-12

Floating-Point Status and Control Register (FPSCR) .............................................. 3-13

Condition Register (CR) ........................................................................................... 3-16

Condition Register CR0 Field Definition ............................................................. 3-17

Condition Register CR1 Field Definition ............................................................. 3-17

Condition Register CRn Field — Compare Instruction ....................................... 3-17

Integer Exception Register (XER) ............................................................................ 3-18

Link Register (LR) .................................................................................................... 3-19

Count Register (CTR) ............................................................................................... 3-19

VEA Register Set — Time Base (TB) .......................................................................... 3-20

OEA Register Set .......................................................................................................... 3-20

Machine State Register (MSR) ................................................................................. 3-20

DAE/Source Instruction Service Register (DSISR) ................................................. 3-22

Data Address Register (DAR) .................................................................................. 3-23

Time Base Facility (TB) — OEA ............................................................................. 3-23

Decrementer Register (DEC) .................................................................................... 3-23

Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23

Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23

General SPRs (SPRG0–SPRG3) .............................................................................. 3-24

Processor Version Register (PVR) ........................................................................... 3-25

Implementation-Specific SPRs ................................................................................. 3-25

EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25

Floating-Point Exception Cause Register (FPECR) ............................................. 3-26

Additional Implementation-Specific Registers ..................................................... 3-27

Instruction Set ............................................................................................................... 3-27

Instruction Set Summary .......................................................................................... 3-28

Recommended Simplified Mnemonics ..................................................................... 3-33

Calculating Effective Addresses ............................................................................... 3-34

Exception Model ........................................................................................................... 3-34

Exception Classes ..................................................................................................... 3-35

Ordered Exceptions ................................................................................................... 3-35

Unordered Exceptions ............................................................................................... 3-35

Precise Exceptions .................................................................................................... 3-36

Exception Vector Table ............................................................................................ 3-36

Instruction Timing ........................................................................................................ 3-37

User Instruction Set Architecture (UISA) .................................................................... 3-39

Computation Modes .................................................................................................. 3-39

Reserved Fields ......................................................................................................... 3-39

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor

MPC564MZP56R2 Related Products

	MPC564MZP56R2	MPC562MZP56R2	MPC564MZP56	MPC563MZP66R2	MPC563MZP56R2
Description	RISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388	RISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388	RISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388	RISC Microcontroller, 32-Bit, FLASH, 66MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388	RISC Microcontroller, 32-Bit, FLASH, 56MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151, BGA-388
package instruction	BGA, BGA388,26X26,40	BGA, BGA388,26X26,40	BGA, BGA388,26X26,40	BGA,	BGA, BGA388,26X26,40
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
Has ADC	NO	NO	NO	NO	NO
Address bus width	24	24	24	24	24
bit size	32	32	32	32	32
maximum clock frequency	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz
DAC channel	NO	NO	NO	NO	NO
DMA channel	NO	NO	NO	NO	NO
External data bus width	32	32	32	32	32
JESD-30 code	S-PBGA-B388	S-PBGA-B388	S-PBGA-B388	S-PBGA-B388	S-PBGA-B388
length	27 mm	27 mm	27 mm	27 mm	27 mm
Number of I/O lines	16	16	16	16	16
Number of terminals	388	388	388	388	388
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
PWM channel	NO	NO	NO	NO	NO
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
ROM programmability	FLASH	FLASH	FLASH	FLASH	FLASH
Maximum seat height	2.55 mm	2.55 mm	2.55 mm	2.55 mm	2.55 mm
speed	56 MHz	56 MHz	56 MHz	66 MHz	56 MHz
Maximum supply voltage	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Nominal supply voltage	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
surface mount	YES	YES	YES	YES	YES
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	27 mm	27 mm	27 mm	27 mm	27 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC
Is it Rohs certified?	incompatible	incompatible	incompatible	-	incompatible
Base Number Matches	1	1	1	1	-

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