A3PE1500-2FGG896ES datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> A3PE1500-2FGG896ES

A3PE1500-2FGG896ES: DescriptionFPGA, 75264 CLBS, 3000000 GATES, PBGA896; Categorysemiconductor Programmable logic devices; File Size5MB，152 Pages; ManufacturerActel; Websitehttp://www.actel.com/

Download Datasheet Parametric View All

A3PE1500-2FGG896ES Overview

FPGA, 75264 CLBS, 3000000 GATES, PBGA896

A3PE1500-2FGG896ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	896
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-896
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN SILVER COPPER
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
organize	75264 CLBS, 3000000 GATES
Number of configurable logic modules	75264
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	3.00E6

Preview

Download Datasheet

View All

v1.0

ProASIC3E Flash Family FPGAs

with Optional Soft ARM

Support

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

to Secure FPGA Contents

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC

3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable

Phase-Shift,

Multiply/Divide,

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 200 MHz)

Delay

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

High-Performance Routing Hierarchy

•

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

ARM Processor Support in ProASIC3E FPGAs

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

Table 1-1 •

ProASIC3E Product Family

ProASIC3E Devices

Cortex-M1 Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

PQFP

FBGA

A3PE600

600 k

13,824

108

Yes

270

PQ208

FG256, FG484

A3PE1500

M1A3PE1500

1.5 M

38,400

270

Yes

444

PQ208

FG484, FG676

A3PE3000

M1A3PE3000

75,264

504

112

Yes

620

PQ208

FG324

FG484, FG896

Notes:

1. Refer to the

Cortex-M1

product brief for more information.

2. The PQ208 package has six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the

ProASIC3 Flash Family FPGAs

handbook.

March 2008

1 – ProASIC3E Device Family Overview

General Description

ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASIC

PLUS®

family. Nonvolatile flash technology gives ProASIC3E

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices

have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and

up to 620 user I/Os.

Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have

Actel ordering numbers that begin with M1A3PE.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications

in the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in

AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3E devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure

design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and

AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your

v1.0

1-1

Recommended Resources

Bidirectional anti-shake circuit

SS0604 touch step dimming light circuit

555 light tone changing circuit

Working circuit of electronic polymer condensation sensor

Automatic car headlight switch

4W backup switching regulated power supply

求助：Assertion Failed! File wincore.cpp,Line 2347 eVC4: WinCE program environment eVC4 Error: Assertion Failed! File wincore.cpp,Line wincore.cpp,Line 2347: Code CWnd* CWnd::GetTopLevelParent() const { if (GetSafeHwnd() == NULL) // no Window attached retur...; ws01103815 Embedded System

Have you ever made an embedded video decoder?: The job I'm taking over now is to use C64x's DSP to make an H.264 decoder, and use ARM as an auxiliary verification. My idea is this: the encoding end is carried out on the computer, and H.264 is used...; langzileo Embedded System

Share Bluetooth speakers/smart wearable gesture recognition sensors: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:50[/i]ISSI Sensor IC is used in Bluetooth speakers/earphones to perform gesture recognition operations through the infrared transmissio...; janbe Mobile and portable

NXP ARM Cortex Microcontroller Technology Seminar (Free): Friends who follow NXP ARM Cortex microcontrollers in the forum are in luck! Not only will you have the opportunity to get a free development board from NXP in the forum, but you will also have the op...; EEWORLD社区 NXP MCU

AVR simulation AD conversion example: Avr simulation AD conversion example, very good...; jianggl007 Microchip MCU

DfuSe firmware download software button description: [i=s] This post was last edited by Chen Shaohua on 2018-6-22 19:50 [/i] DfuSe operation interfaceDfuSe button descriptionMy operation is to download the firmware in the order of 7 8 9 10...; 陈韶华 MicroPython Open Source section

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components