A3P600-FGG144ES datasheet, PDF

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A3P600-FGG144ES: DescriptionFPGA, 24576 CLBS, 1000000 GATES, 350 MHz, PBGA144; Categorysemiconductor Programmable logic devices; File Size6MB，206 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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A3P600-FGG144ES Overview

FPGA, 24576 CLBS, 1000000 GATES, 350 MHz, PBGA144

A3P600-FGG144ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	13× 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-144
Lead-free	Yes
EU RoHS regulations	Yes
state	TRANSFERRED
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array, low PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin silver copper
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
organize	24576 CLBS, 1,000,000 doors
Maximum FCLK clock frequency	350 MHz
Number of configurable logic modules	24576
Programmable logic type	FIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits	1.00E6

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v1.0

ProASIC3 Flash Family FPGAs

with Optional Soft ARM

Support

Features and Benefits

High Capacity

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

†

Clock Conditioning Circuit (CCC) and PLL

†

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X

†

and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase-Shift,

Multiply/Divide,

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Delay

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM-enabled ProASIC

devices) via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Embedded Memory

†

Low Power

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

ARM Processor Support in ProASIC3 FPGAs

• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft

Processor Available with or without Debug

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

ProASIC3 Product Family

ProASIC3 Devices

ARM7 Devices

Cortex-M1 Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

QFN

VQFP

TQFP

PQFP

FBGA

A3P015

A3P030

A3P060

A3P125

A3P250

M1A3P250

250 k

–

6,144

Yes

157

QN132

VQ100

PQ208

FG144/256

PQ208

FG144/256/

484

PQ208

FG144/256/

484

PQ208

FG144/256/

484

A3P400

M1A3P400

400 k

–

9,216

Yes

194

A3P600

M1A3P600

600 k

–

13,824

108

Yes

235

A3P1000

M7A3P1000

M1A3P1000

–

24,576

144

Yes

300

15 k

128

384

–

QN68

30 k

256

768

–

QN132

VQ100

60 k

512

1,536

Yes

QN132

VQ100

TQ144

FG144

125 k

1,024

3,072

Yes

133

QN132

VQ100

TQ144

PQ208

FG144

Notes:

1. Refer to the

CoreMP7

datasheet or

Cortex-M1

product brief for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the

ProASIC3E Flash Family FPGAs

handbook.

5. The M1A3P250 device does not support this package.

† A3P015 and A3P030 devices do not support this feature.

February 2008

‡ Supported only by A3P015 and A3P030 devices.

1 – ProASIC3 Device Family Overview

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASIC

PLUS®

family. Nonvolatile flash technology gives ProASIC3

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and

A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices

have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do

not support AES decryption.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in

the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES

decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3 devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure

design verification is possible.

ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the

ARM core must be protected at all times, AES encryption is always on for the core logic, so

bitstreams are always encrypted. There is no user access to encryption for the FlashROM

programming data.

v1.0

1-1

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