December 2003
rev 1.0
LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15 dB of EMI suppression
Generates a low EMI spread spectrum clock of the
input frequency
50 MHz to 170 MHz input frequency range
Optimized for 54MHz, 65MHz, 81MHz, 140MHz,
and 162MHz pixel clock frequencies
Internal loop filter minimizes external components
and board space
8 selectable spread ranges, up to +/- 2.2%
SSON# control pin for spread spectrum enable
and disable options
2 selectable modulation rates
Low cycle-to-cycle jitter
3.3V operating voltage
16 mA output drives
TTL or CMOS compatible outputs
Ultra low power CMOS design
Supports most mobile graphic accelerator and
LCD timing controller specifications
Available in 8 pin SOIC and TSSOP
P2040C
Product Description
The P2040C is a selectable spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2040C
reduces
electromagnetic
interference (EMI) at the clock source which provides
system wide reduction of EMI of all clock dependent
signals.
The P2040C allows significant system cost
savings by reducing the number of circuit board layers
and shielding that are traditionally required to pass EMI
regulations.
The P2040C uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all-digital method.
The P2040C modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock
and, more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
Applications
The P2040C is targeted towards digital flat panel
applications for Notebook PCs, Palm-size PCs,
Office Automation Equipments, and LCD Monitors.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
December 2003
rev 1.0
Block Diagram
P2040C
SR0 SR1 MRA SSON#
VDD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Pin Configuration
CLKIN
MRA
SR1
VSS
1
2
8
7
VDD
SR0
ModOUT
SSON#
P2040C
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up
resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal
pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
Power supply for the entire chip (3.3V)
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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December 2003
rev 1.0
Modulation Selection (Commercial) – Table 1
MRA
SR1
SR0
Spreading Range
Modulation Rate
P2040C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
54 MHz
+/-1.4%
+/-2.0%
+/-1.1%
+/-1.8%
+/-1.3%
+/-2.2%
+/-1.4%
+/-2.1%
65 MHz
+/-1.2%
+/-1.9%
+/-0.9%
+/-1.5%
+/-1.3%
+/-2.1%
+/-1.3%
+/-2.1%
81 MHz
+/-1.0%
+/-1.6%
+/-0.5%
+/-1.0%
+/-1.3%
+/-2.1%
+/-1.4%
+/-2.1%
108 MHz
+/-0.8%
+/-1.2%
+/-0.4%
+/-0.6%
+/-1.2%
+/-1.9%
+/-1.2%
+/-2.0%
162 MHz
+/-0.4%
+/-0.8%
+/-0.3%
+/-0.4%
+/-1.1%
+/-1.8%
+/-0.9%
+/-1.4%
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
Spread Spectrum Selection
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency (Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example:
P2040C is designed for high resolution flat panel applications and is able to support panel frequencies
from 54MHz to 170MHz. For a 65MHz pixel clock frequency, a spreading selection of MRA=0, SR1=1 and SR0=1
provides a percentage deviation of +/-1.50% (see Table 1). This results in frequency on ModOUT being swept
from 64.03MHz to 65.98MHz at a modulation rate of 50.77KHz (see Table 1). This particular example (see Figure
below) given here is a common EMI reduction method for notebook LCD panel and has already been
implemented by most of the leading OEM and mobile graphic accelerator manufacturers.
P2040C Application Schematic for Mobile LCD Graphics
65MHz from graphics accelerator
1
CLKIN
MRA
SR1
VSS
VDD
SR0
ModOUT
SSON#
8
2
7
0.1µF
Modulated 65MHz signal with
±0.75 deviation and modulation
rate of 56.24KHz. This signal is
connected back to the spread
+3.3V
spectrum input pin (SSIN) of the
graphics accelerator.
3
6
4
5
P2040C
Digital control for the SS enable
or disable
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
December 2003
rev 1.0
EMC Software Simulation
P2040C
By using Alliance EMI-Lator®
1
electromagnetic interference simulation software, radiated system level EMI
analysis can be made easier to allow a quantitative assessment of EMI reduction products. The simulation engine
of this EMC software has already been characterized to correlate to the electrical characteristics of the Alliance
EMI reduction ICs. The following illustration is an example of the simulation result. Please visit our website at
www.alsc.com
for information on how to obtain a free copy and a demonstration of the EMI-Lator simulation
software.
Simulation results From EMI-Lator®
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
December 2003
rev 1.0
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
Storage Temperature
Operating Temperature
Parameter
Voltage on any pin with respect to GND
Rating
-0.5 to +7.0
-65 to +125
0 to +70
P2040C
Unit
V
ºC
ºC
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings
for prolonged periods of time may affect device reliability.
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Parameter
Input Low Voltage
Input High Voltage
Input Low Current (pull-up resistor on inputs SR0, 1
and MRA)
Input High Current (pull-down resistor on input
SSON#)
Output Low Voltage (VDD=3.3V, IOL = 20 mA)
Output High Voltage (VDD=3.3V, IOH = 20 mA)
Static Supply Current
Dynamic Supply Current (3.3V and 15 pF loading)
Operating Voltage
Power Up Time (First locked clock cycle after power
up)
Clock Output Impedance
Min
GND – 0.3
2.0
-
-
-
2.5
-
9
2.7
Typ
-
-
-
-
-
-
0.6
16
3.3
0.18
50
Max
0.8
V
DD
+ 0.3
-35
35
0.4
-
-
22
3.7
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
t
LH
*
t
HL *
t
JC
t
D
Parameter
Input Frequency, P2040C
Output Rise Time (0.8V to 2.0V)
Output Fall Time (2.0V to 0.8V)
Jitter (cycle to cycle)
Output Duty Cycle
Min
50
0.7
0.6
-
45
Typ
120
0.9
0.8
-
50
Max
175
1.1
1.0
360
55
Unit
MHz
ns
ns
ps
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Package Information
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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