A2040C-08TR datasheet, PDF - EEWORLD Datasheet

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A2040C-08TR: DescriptionPLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8; Categorylogic logic; File Size493KB，9 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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A2040C-08TR Overview

PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8

A2040C-08TR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	SOIC
package instruction	TSSOP,
Contacts	8
Reach Compliance Code	unknown
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.4 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	1
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.7 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm

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December 2003

rev 1.0

LCD Panel EMI Reduction IC

Features

FCC approved method of EMI attenuation.

Provides up to 15 dB of EMI suppression

Generates a low EMI spread spectrum clock of the

input frequency

50 MHz to 170 MHz input frequency range

Optimized for 54MHz, 65MHz, 81MHz, 140MHz,

and 162MHz pixel clock frequencies

Internal loop filter minimizes external components

and board space

8 selectable spread ranges, up to +/- 2.2%

SSON# control pin for spread spectrum enable

and disable options

2 selectable modulation rates

Low cycle-to-cycle jitter

3.3V operating voltage

16 mA output drives

TTL or CMOS compatible outputs

Ultra low power CMOS design

Supports most mobile graphic accelerator and

LCD timing controller specifications

Available in 8 pin SOIC and TSSOP

P2040C

Product Description

The P2040C is a selectable spread spectrum frequency

modulator designed specifically for digital flat panel

applications.

The

P2040C

reduces

electromagnetic

interference (EMI) at the clock source which provides

system wide reduction of EMI of all clock dependent

signals.

The P2040C allows significant system cost

savings by reducing the number of circuit board layers

and shielding that are traditionally required to pass EMI

regulations.

The P2040C uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented in a proprietary all-digital method.

The P2040C modulates the output of a single PLL in

order to “spread” the bandwidth of a synthesized clock

and, more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called “spread

spectrum clock generation”.

Applications

The P2040C is targeted towards digital flat panel

applications for Notebook PCs, Palm-size PCs,

Office Automation Equipments, and LCD Monitors.

Alliance Semiconductor

2575, Augustine Drive

•

Santa Clara, CA

•

Tel: 408.855.4900

•

Fax: 408.855.4999

•

www.alsc.com

Notice: The information in this document is subject to change without notice.

A2040C-08TR Related Products

	A2040C-08TR	I2040C-08TT	A2040C-08SR	A2040C-08ST	I2040C-08ST	A2040C-08TT
Description	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8	PLL Based Clock Driver, 2040 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 4.40 MM, TSSOP-8	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8	PLL Based Clock Driver, 2040 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	TSSOP,	TSSOP,	SOP,	SOP,	SOP,	TSSOP,
Contacts	8	8	8	8	8	8
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0	e0	e0	e0	e0
length	4.4 mm	4.4 mm	4.92 mm	4.92 mm	4.9 mm	4.4 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1	1	1
Number of terminals	8	8	8	8	8	8
Actual output times	1	1	1	1	1	1
Maximum operating temperature	125 °C	85 °C	125 °C	125 °C	85 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	SOP	SOP	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm	1.8 mm	1.8 mm	1.75 mm	1.1 mm
Maximum supply voltage (Vsup)	3.7 V	3.6 V	3.7 V	3.7 V	3.6 V	3.7 V
Minimum supply voltage (Vsup)	2.7 V	3 V	2.7 V	2.7 V	3 V	2.7 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL	AUTOMOTIVE
Terminal surface	TIN LEAD	Tin/Lead (Sn/Pb)	TIN LEAD	TIN LEAD	Tin/Lead (Sn/Pb)	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm	3.95 mm	3.95 mm	3.91 mm	3 mm
Base Number Matches	-	1	1	1	1	-

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