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NE8500295-8

Description
RF Power Field-Effect Transistor, 1-Element, C Band, Gallium Arsenide, N-Channel, Metal Semiconductor FET, HERMETIC SEALED PACKAGE-2
CategoryDiscrete semiconductor    The transistor   
File Size59KB,6 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

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NE8500295-8 Overview

RF Power Field-Effect Transistor, 1-Element, C Band, Gallium Arsenide, N-Channel, Metal Semiconductor FET, HERMETIC SEALED PACKAGE-2

NE8500295-8 Parametric

Parameter NameAttribute value
package instructionHERMETIC SEALED PACKAGE-2
Reach Compliance Codeunknown
Other featuresHIGH RELIABILITY
Shell connectionSOURCE
ConfigurationSINGLE
Minimum drain-source breakdown voltage10 V
Maximum drain current (ID)2.5 A
FET technologyMETAL SEMICONDUCTOR
highest frequency bandC BAND
JESD-30 codeR-CDFM-F2
Number of components1
Number of terminals2
Operating modeDEPLETION MODE
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formFLANGE MOUNT
Polarity/channel typeN-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal formFLAT
Terminal locationDUAL
transistor applicationsAMPLIFIER
Transistor component materialsGALLIUM ARSENIDE
Base Number Matches1
2 WATT C-BAND
POWER GaAs MESFET
FEATURES
• CLASS A OPERATION
• HIGH EFFICIENCY:
η
ADD
39% TYP
• BROADBAND CAPABILITY
• PACKAGE OPTIONS:
Chip
Hermetic Package
• PARTIALLY MATCHED INPUT FOR PACKAGED
DEVICES
• PROVEN RELIABILITY
NE8500200
NE8500295-4
NE8500295-6
NE8500295-8
PART
NUMBER
NE85002
SERIES
SELECTION CHART
TYPICAL PERFORMANCE
FREQUENCY
G
L
RANGE
(dBm)
(GHz)
(dB)
P
OUT
33.8 MIN
33.8 MIN
33.8 MIN
33.5 MIN
2.0 to 10
3.5 to 4.5
5.5 to 6.5
7.5 to 8.5
8.0 MIN
10.5 MIN
9.5 MIN
8.0 MIN
DESCRIPTION
The NE8500295 power GaAs FET covers the 3.5 to 8.5 GHz
frequency range with three different Class A, 2 W partially
matched devices. Each packaged device has an input lumped
element matching network.
The NE8500200 is the six-cell recessed gate chip used in the
"95" package. The device incorporates a Ti-Al gate structure,
SiO
2
glassivation and plated heat sink technology.
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
I
DSS
V
P
g
m
BV
GDO
I
GS
R
TH
P
TEST2
NE8500200
1
00 (CHIP)
NE8500295-4
95
NE8500295-6
95
NE8500295-8
95
TYP MAX
1900
-1.0
600
18
2.4
15
-2.4
2.4
15
PARAMETERS AND CONDITIONS UNITS MIN
Saturated Drain Current
V
DS
= 2.5 V, V
GS
= 0 V
Pinch-off Voltage
V
DS
= 2.5 V, I
D
= 8 mA
Transconductance
V
DS
= 2.5 V, I
D
= I
DSS
Drain-Gate Breakdown Voltage
I
GD
= 8 mA
Gate to Source Current, V
DS
= 10 V,
I
DSQ
= 450 mA, P
OUT
= P
TEST
Power Output at Test Point
V
DS
= 10 V, I
DS
= 450 mA set
P
IN
= 27.0 dBm
P
IN
= 24.5 dBm
P
IN
= 25.5 dBm
Linear Gain
V
DS
= 10 V, I
DS
= 450 mA
Power Added Efficiency
at P
TEST
mA
V
mS
V
mA
18
-2.4
950
-3.0
TYP MAX MIN
1900
-1.0
600
18
2.4
10
15
-2.4
950
-3.0
TYP MAX MIN
1900
-1.0
600
18
2.4
15
-2.4
950
-3.0
TYP MAX MIN
1900
-1.0
600
950
-3.0
Thermal Resistance (Channel-to-Case)
°C/W
dBm
dBm
dBm
33.8
33.8
33.8
33.5
G
L
η
ADD3
dB
%
8.0
9.0
42
10.5
47
9.5
45
8.0
39
Notes:
1. Six-cell chip: all cells are used. RF performance of the chip is
determined by packaging 10 chips per wafer. Wafer rejection
criteria for standard devices are 2 rejects per 10 samples.
2. This is a production test. Test frequencies are: -4 @ 4.2 GHz,
-6 @ 6.5 GHz, -8 and NE8500200 @ 8.5 GHz.
P
OUT
- P
IN
3.
η
ADD = V
DS
- I
D
x 100%
California Eastern Laboratories
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