SN54/74LS122
SN54/74LS123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS
These dc triggered multivibrators feature pulse width control by three meth-
ods. The basic pulse width is programmed by selection of external resistance
and capacitance values. The LS122 has an internal timing resistor that allows
the circuits to be used with only an external capacitor. Once triggered, the ba-
sic pulse width may be extended by retriggering the gated low-level-active (A)
or high-level-active (B) inputs, or be reduced by use of the overriding clear.
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS
LOW POWER SCHOTTKY
•
•
•
•
•
Overriding Clear Terminates Output Pulse
Compensated for VCC and Temperature Variations
DC Triggered from Active-High or Active-Low Gated Logic Inputs
Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
Internal Timing Resistors on LS122
16
1
J SUFFIX
CERAMIC
CASE 620-09
SN54 / 74LS123
(TOP VIEW)
(SEE NOTES 1 THRU 4)
1 R
ext/
V
CC
16
C
ext
15
1
C
ext
14
1Q
13
2Q
12
2
CLR
2B
10
2A
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
11
Q
CLR
Q
CLR
Q
Q
16
1
6
2
7
2
R
ext/
C
ext
8
GND
D SUFFIX
SOIC
CASE 751B-03
1
1A
2
1B
3
1
CLR
4
1Q
5
2Q
C
ext
J SUFFIX
CERAMIC
CASE 632-08
14
1
SN54 / 74LS122
(TOP VIEW)
(SEE NOTES 1 THRU 4)
R
ext/
V
CC
14
C
ext
13
NC
12
C
ext
11
NC
10
R
int
9
Q
8
R
int
Q
14
1
N SUFFIX
PLASTIC
CASE 646-06
CLR
Q
1
A1
2
A2
3
B1
4
B2
5
CLR
6
Q
7
GND
14
1
D SUFFIX
SOIC
CASE 751A-02
NC
NO INTERNAL CONNECTION.
NOTES:
1. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
2. To use the internal timing resistor of the LS122, connect Rint to VCC.
3. For improved pulse width accuracy connect an external resistor between Rext/Cext and
VCC with Rint open-circuited.
4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext
and VCC.
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-197
SN54/74LS122
•
SN54/74LS123
LS122
FUNCTIONAL TABLE
INPUTS
CLEAR
L
X
X
X
H
H
H
H
H
H
H
↑
↑
A1
X
H
X
X
L
L
X
X
H
↓
↓
L
X
A2
X
H
X
X
X
X
L
L
↓
↓
H
X
L
B1
X
X
L
X
↑
H
↑
H
H
H
H
H
H
B2
X
X
X
L
H
↑
H
↑
H
H
H
H
H
OUTPUTS
Q
L
L
L
L
Q
H
H
H
H
CLEAR
L
X
X
H
H
↑
LS123
FUNCTIONAL TABLE
INPUTS
A
X
H
X
L
↓
L
B
X
X
L
↑
H
H
OUTPUTS
Q
L
L
L
Q
H
H
H
TYPICAL APPLICATION DATA
The output pulse tW is a function of the external compo-
nents, Cext and Rext or Cext and Rint on the LS122. For values
of Cext
≥
1000 pF, the output pulse at VCC = 5.0 V and VRC =
5.0 V (see Figures 1, 2, and 3) is given by
tW = K Rext Cext where K is nominally 0.45
If Cext is on pF and Rext is in kΩ then tW is in nanoseconds.
The Cext terminal of the LS122 and LS123 is an internal
connection to ground, however for the best system perfor-
mance Cext should be hard-wired to ground.
Care should be taken to keep Rext and Cext as close to the
monostable as possible with a minimum amount of inductance
between the Rext/Cext junction and the Rext/Cext pin. Good
groundplane and adequate bypassing should be designed
into the system for optimum performance to insure that no
false triggering occurs.
It should be noted that the Cext pin is internally connected
to ground on the LS122 and LS123, but not on the LS221.
Therefore, if Cext is hard-wired externally to ground, substitu-
tion of a LS221 onto a LS123 socket will cause the LS221 to
become non-functional.
The switching diode is not needed for electrolytic capaci-
tance application and should not be used on the LS122 and
LS123.
To find the value of K for Cext
≥
1000 pF, refer to Figure 4.
Variations on VCC or VRC can cause the value of K to change,
as can the temperature of the LS123, LS122. Figures 5 and
6 show the behavior of the circuit shown in Figures 1 and 2 if
separate power supplies are used for VCC and VRC. If VCC is
tied to VRC, Figure 7 shows how K will vary with VCC and
temperature. Remember, the changes in Rext and Cext with
temperature are not calculated and included in the graph.
As long as Cext
≥
1000 pF and 5K
≤
Rext
≤
260K
(SN74LS122 / 123) or 5K
≤
Rext
≤
160 K (SN54LS122 / 123),
the change in K with respect to Rext is negligible.
If Cext
≤
1000 pF the graph shown on Figure 8 can be used
to determine the output pulse width. Figure 9 shows how K will
change for Cext
≤
1000 pF if VCC and VRC are connected to the
same power supply. The pulse width tW in nanoseconds is
approximated by
tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext
In order to trim the output pulse width, it is necessary to
include a variable resistor between VCC and the Rext/Cext pin
or between VCC and the Rext pin of the LS122. Figure 10, 11,
and 12 show how this can be done. Rext remote should be kept
as close to the monostable as possible.
Retriggering of the part, as shown in Figure 3, must not
occur before Cext is discharged or the retrigger pulse will not
have any effect. The discharge time of Cext in nanoseconds is
guaranteed to be less than 0.22 Cext (pF) and is typically 0.05
Cext (pF).
For the smallest possible deviation in output pulse widths
from various devices, it is suggested that Cext be kept
≥
1000 pF.
FAST AND LS TTL DATA
5-198
SN54/74LS122
•
SN54/74LS123
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
LS122
ICC
Power Supply Current
LS123
20
– 20
– 0.4
–100
11
mA
VCC = MAX
0.35
0.5
20
IIH
IIL
IOS
V
µA
mA
mA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tW min
tWQ
Parameter
Propagation Delay, A to Q
Propagation Delay, A to Q
Propagation Delay, B to Q
Propagation Delay, B to Q
Propagation Delay, Clear to Q
Propagation Delay, Clear to Q
A or B to Q
A to B to Q
4.0
Min
Typ
23
32
23
34
28
20
116
4.5
Max
33
ns
45
44
ns
56
45
ns
27
200
5.0
ns
µs
Cext = 1000 pF, Rext = 10 kΩ,
CL = 15 pF, RL = 2.0 kΩ
Rext = 5.0 kΩ
RL = 2.0 kΩ
Cext = 0
CL = 15 pF
Unit
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
Pulse Width
Parameter
Min
40
Typ
Max
Unit
ns
Test Conditions
FAST AND LS TTL DATA
5-200
京公网安备 11010802033920号
EEWORLD
