EEWORLDEEWORLDEEWORLD

Part Number

Search

74LS85

Description
LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16
Categorysemiconductor    logic   
File Size52KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

74LS85 Overview

LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16

74LS85 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals16
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
Rated supply voltage5
Minimum supply/operating voltage4.75 V
Maximum supply/operating voltage5.25 V
Processing package description0.300 INCH, PLASTIC, MS-001, DIP-16
stateActive
Logic IC typeMAGNITUDE COMPARATOR
seriesLS
jesd_30_codeR-PDIP-T16
jesd_609_codee0
moisture_sensitivity_levelNOT SPECIFIED
Number of digits4
Output polarityTRUE
Packaging MaterialsPLASTIC/EPOXY
ckage_codeDIP
packaging shapeRECTANGULAR
Package SizeIN-LINE
eak_reflow_temperature__cel_NOT SPECIFIED
propagation delay TPD42 ns
qualification_statusCOMMERCIAL
seated_height_max5.08 mm
surface mountNO
CraftsmanshipTTL
Temperature levelCOMMERCIAL
terminal coatingTIN LEAD
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
ime_peak_reflow_temperature_max__s_NOT SPECIFIED
length19.3 mm
width7.62 mm
dditional_featureCASCADABLE
DM74LS85 4-Bit Magnitude Comparator
August 1986
Revised March 2000
DM74LS85
4-Bit Magnitude Comparator
General Description
These 4-bit magnitude comparators perform comparison of
straight binary or BCD codes. Three fully-decoded deci-
sions about two, 4-bit words (A, B) are made and are exter-
nally available at three outputs. These devices are fully
expandable to any number of bits without external gates.
Words of greater length may be compared by connecting
comparators in cascade. The A
>
B, A
<
B, and A
=
B out-
puts of a stage handling less-significant bits are connected
to the corresponding inputs of the next stage handling
more-significant bits. The stage handling the least-
significant bits must have a high-level voltage applied to
the A
=
B input. The cascading path is implemented with
only a two-gate-level delay to reduce overall comparison
times for long words.
Features
s
Typical power dissipation 52 mW
s
Typical delay (4-bit words) 24 ns
Ordering Code:
Order Number
DM74LS85M
DM74LS85N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006379
www.fairchildsemi.com

74LS85 Related Products

74LS85 DM74LS85 DM74LS85M DM74LS85N
Description LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16
Number of functions 1 1 1 1
Number of terminals 16 16 16 16
Maximum operating temperature 70 Cel 70 Cel 70 °C 70 °C
series LS LS LS LS
Number of digits 4 4 4 4
Output polarity TRUE TRUE TRUE TRUE
surface mount NO NO YES NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE THROUGH-HOLE GULL WING THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL
length 19.3 mm 19.3 mm 9.9 mm 19.305 mm
width 7.62 mm 7.62 mm 3.9 mm 7.62 mm

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 51  629  103  1080  1611  2  13  3  22  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号