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DM74LS85N

Description
LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16
Categorylogic    logic   
File Size52KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS85N Overview

LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16

DM74LS85N Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other featuresCASCADABLE
seriesLS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeMAGNITUDE COMPARATOR
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)42 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
DM74LS85 4-Bit Magnitude Comparator
August 1986
Revised March 2000
DM74LS85
4-Bit Magnitude Comparator
General Description
These 4-bit magnitude comparators perform comparison of
straight binary or BCD codes. Three fully-decoded deci-
sions about two, 4-bit words (A, B) are made and are exter-
nally available at three outputs. These devices are fully
expandable to any number of bits without external gates.
Words of greater length may be compared by connecting
comparators in cascade. The A
>
B, A
<
B, and A
=
B out-
puts of a stage handling less-significant bits are connected
to the corresponding inputs of the next stage handling
more-significant bits. The stage handling the least-
significant bits must have a high-level voltage applied to
the A
=
B input. The cascading path is implemented with
only a two-gate-level delay to reduce overall comparison
times for long words.
Features
s
Typical power dissipation 52 mW
s
Typical delay (4-bit words) 24 ns
Ordering Code:
Order Number
DM74LS85M
DM74LS85N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006379
www.fairchildsemi.com

DM74LS85N Related Products

DM74LS85N 74LS85 DM74LS85 DM74LS85M
Description LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16 LS SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP16
series LS LS LS LS
length 19.305 mm 19.3 mm 19.3 mm 9.9 mm
Number of digits 4 4 4 4
Number of functions 1 1 1 1
Number of terminals 16 16 16 16
Maximum operating temperature 70 °C 70 Cel 70 Cel 70 °C
Output polarity TRUE TRUE TRUE TRUE
surface mount NO NO NO YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE GULL WING
Terminal location DUAL DUAL DUAL DUAL
width 7.62 mm 7.62 mm 7.62 mm 3.9 mm
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