INTEGRATED CIRCUITS
74LV4040
12-stage binary ripple counter
Product specification
IC24 Data Handbook
1998 Jun 23
Philips
Semiconductors
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
FEATURES
•
Optimized for Low Voltage applications: 1.0 to 5.5V
•
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
•
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
•
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
•
Frequency dividing circuits
•
Time delay circuits
•
Control counters
•
Output capability: standard
•
I
CC
category: MSI
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
=t
f
v2.5
ns
SYMBOL
PARAMETER
Propagation delay
CP to Q
0
Q
n
to Q
n+1
MR to Q
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV4040 is a low–voltage Si–gate CMOS device and is pin
and function compatible with 74HC/HCT4040.
The 74LV4040 is a 12-stage binary ripple counter with a click input
(CP), an overriding asynchronous master reset input (MR) and
twelve fully buffered parallel outputs (Q
0
to Q
11
). The counter is
advanced on the HIGH-to-LOW transition of CP. A HIGH on MR
clears all counter stages and forces all outputs LOW, independent of
the state of CP.
Each counter stage is a static toggle flip-flop.
CONDITIONS
C
L
= 15pF
V
CC
= 3.3V
TYPICAL
12
7
16
100
3.5
UNIT
t
PHL
/t
PLH
f
max
C
I
C
PD
ns
MHz
pF
pF
Notes 1 and 2
30
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
x f
i
)S
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
V
CC2
f
o
) = sum of the outputs.
S
(C
L
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV4040 N
74LV4040 D
74LV4040 DB
74LV4040 PW
NORTH AMERICA
74LV4040 N
74LV4040 D
74LV4040 DB
74LV4040PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 Jun 23
2
853-2075 19619
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
PIN CONFIGURATION
LOGIC SYMBOL
Q
0
9
7
6
5
3
2
4
13
12
14
15
1
Q
11
Q
5
Q
4
Q
6
Q
3
Q
2
Q
1
GND
1
2
3
4
5
6
7
8
16 V
CC
15 Q
10
14 Q
9
13 Q
7
12 Q
8
11 MR
10 CP
9
Q
0
11
MR
10
CP
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
SV00316
SV00317
Figure 1. Pin configuration
Figure 3. Logic symbol
PIN DESCRIPTION
PIN
NUMBER
9, 7, 6, 5, 3,
2, 4, 13, 12,
14, 15, 1
8
10
11
16
SYMBOL
FUNCTION
FUNCTIONAL DIAGRAM
Q
0
to Q
11
GND
CP
MR
V
CC
Parallel outputs
Ground (0V)
Clock input (HIGH-to-LOW, edge-
triggered)
Master reset input (active HIGH)
Positive supply voltage
10
11
CP
T
12-STAGE COUNTER
MR
C
D
Q
0
Q
1
9
7
Q
2
Q
3
5
5
Q
4
3
Q
5
2
Q
6
4
Q
7
13
Q
8
12
Q
9
14
Q
10
Q
11
15
1
LOGIC SYMBOL (IEEE/IEC)
SV00319
CTR12
10
11
+
CT=0
0
9
7
5
5
3
2
CT
4
13
12
14
15
11
1
MR
CP
FF0
Q
T
Q
R
D
T
Q
R
D
FF3
Q
FF11
Q
T
Q
R
D
Figure 4. Functional diagram
LOGIC DIAGRAM
SV00318
Figure 2. IEC Logic symbol
Q0
Q1
Q11
SV00320
Figure 5. Logic diagram
1998 Jun 23
3
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
1
CP INPUT
2
4
8
16
32
64
128
256
512
1.024
2.048
4.096
MR INPUT
Q
0
OUTPUT
Q
1
OUTPUT
Q
2
OUTPUT
Q
3
OUTPUT
Q
4
OUTPUT
Q
5
OUTPUT
Q
6
OUTPUT
Q
7
OUTPUT
Q
8
OUTPUT
Q
9
OUTPUT
Q
10
OUTPUT
Q
11
OUTPUT
SV00310
Figure 6. Timing diagram
FUNCTION TABLE
INPUTS
CP
°
±
X
MR
L
L
H
OUTPUTS
Q
0
, Q
3
to Q
13
no change
count
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
°
= LOW -to-HIGH clock transition
±
= HIGH-to-LOW clock transition
1998 Jun 23
4
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
–standard outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
Input voltage
Output voltage
Operating ambient temperature range in free
air
Input rise and fall times
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
PARAMETER
DC supply voltage
CONDITIONS
See Note
1
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
–
–
TYP.
3.3
–
–
MAX
5.5
V
CC
V
CC
+85
+125
500
200
100
50
UNIT
V
V
V
°C
t
r
, t
f
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
1998 Jun 23
5
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