2K
X76F200
Secure SerialFlash
256 x 8 Bit
FEATURES
• 64-bit password security
• One array (240 bytes) two passwords (16 bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (RST input)
• 8 byte sector write mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—2.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead PDIP, SOIC, TSSOP, smart card and
smart card module
DESCRIPTION
The X76F200 is a password access security supervi-
sor, containing one 1920-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F200 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
The X76F200 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
BLOCK DIAGRAM
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Data Transfer
The X76F200 utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
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SCL
SDA
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Array Access
Enable
240 Byte
EEPROM Array
Password Array
and Password
Verification Logic
Interface
Logic
RST
ISO Reset
Response Register
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Retry Counter
Erase Logic
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Characteristics subject to change without notice.
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X76F200
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
the X76F200 will output 32 bits of fixed data which con-
forms to the standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur. See Figure 7. If power is
interrupted during the response to reset, it will abort,
and the part will return to standby state. The response
to reset is “mask programmable” only!
DEVICE OPERATION
If the X76F200 is in a nonvolatile write cycle, a “no ACK”
(SDA = High) response will be issued in response to
loading of the command byte. If a stop is issued prior to
the nonvolatile write cycle, the write operation will be
terminated; the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
SDA
SCL
RST
V
CC
V
SS
NC
P
V
CC
NC
NC
V
SS
V
SS
NC
SDA
NC
V
CC
NC
NC
V
SS
PIN CONFIGURATION
PDIP
1
2
3
4
SOIC
1
2
3
4
TSSOP
1
2
3
4
8
7
6
5
RST
SCL
SDA
NC
8
7
6
5
V
CC
RST
SCL
NC
V
CC
RST
SCL
NC
GND
NC
SDA
NC
8
7
6
5
RST
SCL
SDA
NC
Smart Card
O
The basic method of communication for the device is to
generate a start condition, then to transmit a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge polling.) The data transfer
occurs after the correct password is accepted and an
ACK polling has occurred.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
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There are two primary modes of operation for the
X76F200; protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
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The X76F200 memory array consists of thirty 8-byte
sectors. Read or write access to the array always
begins at the first address of the sector. Read opera-
tions then can continue indefinitely. Write operations
must total 8 bytes.
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After each transaction is completed, the X76F200 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
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Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Ground
Supply Voltage
No Connect
Characteristics subject to change without notice.
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X76F200
Figure 1. X76F200 Device Operation
Load Command/Address Byte
Verify Password
Acceptance By
Use Of ACK Polling
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
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Device Protocol
The X76F200 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F200 will be considered a
slave in all applications.
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Retry Counter
The X76F200 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of
the passwords are cleared to “0”. If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
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Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F200 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F200 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
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Read/Write
Data Bytes
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence, and will leave the device in the
standby power mode. As with starts, stops are inhib-
ited when outputting data and while a write is in
progress.
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Load 8-Byte
Password
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
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Characteristics subject to change without notice.
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Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F200 continuously monitors the SDA
and SCL lines for the start condition, and will not
respond to any command until this condition is met.
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X76F200
Figure 2. Data Validity
SCL
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
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Sector Write
Sector Read
Change Write Password
Change Read Password
Table 1. X76F200 Instruction Set
Command After Start
1 0 S
4
S
3
S
2
S
1
S
0
0
1 0 S
4
S
3
S
2
S
1
S
0
1
11111100
11111110
01010101
Command Description
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Stop Condition
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Password ACK Command
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command, followed by the password and the data
bytes transferred (illustrated in Figure 4). The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a
sector, and eight bytes must be transferred. After the
last byte to be transferred is acknowledged a stop con-
dition is issued, which starts the nonvolatile write cycle.
If more or less than 8 bytes are transferred, the data in
the sector remains unchanged.
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Illegal command codes will be disregarded. The part
will respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera-
tions require a password.
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ACK Polling
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F200 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition, followed by the new command code of 8 bits
(1st byte of the protocol.) If the X76F200 is still busy
with the nonvolatile write operation, it will issue a “no-
ACK” in response. If the nonvolatile write operation has
completed, an “ACK” will be returned, and the host can
then proceed with the rest of the protocol.
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Password Used
Write
Read
Write
Write
None
Characteristics subject to change without notice.
SDA
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X76F200
Data ACK Polling Sequence
Write Sequence
Completed
Enter ACK Polling
Password ACK Polling Sequence
Password Load
Completed
Enter ACK Polling
Issue New
Command Code
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ACK
Returned?
YES
PROCEED
NO
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F200
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular Acknowledge polling, the user can either
time out for 10ms, and then issue the ACK polling once,
or continuously loop as described in the flow.
If the password inserted was correct, then an “ACK”
will be returned once the nonvolatile cycle in response
to the password ACK polling sequence is over.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations, but with a different command code.
Sector Read
With sector read, a sector address is supplied with the
read command. Once the password has been
acknowledged, data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A
read operation always begins at the first byte in the
sector, but may stop at any time. Random accesses to
the array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array, and data
can continue to be read out. After the last bit has been
read, a stop condition is generated without sending a
preceding acknowledge. (See Figure 6.)
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If the password inserted is incorrect, then a “no ACK”
will be returned even if the nonvolatile cycle is over.
Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed. (See Figure 5.)
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Issue Password
ACK Command
ACK
Returned?
NO
YES
PROCEED
Characteristics subject to change without notice.
Issue START
Issue START
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