74LVT32374 • 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
April 2001
Revised June 2002
74LVT32374 • 74LVTH32374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT32374 and LVTH32374 contain thirty-two non-
inverting D-type flip-flops with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. A buffered clock (CP) and Output Enable (OE)
are common to each byte and can be shorted together for
full 32-bit operation.
The LVTH32374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT32374 and LVTH32374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32374)
s
Also available without bushold feature (74LVT32374)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
−
32 mA/
+
64 mA
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
74LVT32374G
(Note 1)(Note 2)
74LVTH32374G
(Note 1)(Note 2)
Package
Number
BGA96A
(Preliminary)
BGA96A
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500452
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74LVT32374 • 74LVTH32374
Connection Diagram
Pin Descriptions
Pin Names
OE
n
CP
n
I
0
–I
31
O
0
–O
31
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
(Top Thru View)
J
K
L
M
N
P
R
T
O
1
O
3
O
5
O
7
O
9
O
11
O
13
O
14
O
17
O
19
O
21
O
23
O
25
O
27
O
29
O
30
2
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
15
O
16
O
18
O
20
O
22
O
24
O
26
O
28
O
31
3
OE
1
GND
V
CC1
GND
GND
V
CC1
GND
OE
2
OE
3
GND
V
CC2
GND
GND
V
CC2
GND
OE
4
4
CP
1
GND
V
CC1
GND
GND
V
CC1
GND
CP
2
CP
3
GND
V
CC2
GND
GND
V
CC2
GND
CP
4
5
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
15
I
16
I
18
I
20
I
22
I
24
I
26
I
28
I
31
6
I
1
I
3
I
5
I
7
I
9
I
11
I
13
I
14
I
17
I
19
I
21
I
23
I
25
I
27
I
29
I
30
Functional Description
The LVT32374 and LVTH32374 consist of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins
can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common
to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their
individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP
n
) transition. With
the Output Enable (OE
n
) LOW, the contents of the flip-flops are available at the outputs. When OE
n
is HIGH, the outputs go
to the high impedance state. Operation of the OE
n
input does not affect the state of the flip-flops.
Truth Tables
Inputs
CP
1
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
O
o
Z
Outputs
I
16
–I
23
H
L
X
X
O
16
–O
23
H
L
O
o
Z
CP
4
CP
2
Inputs
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
O
o
Z
Outputs
I
24
–I
31
H
L
X
X
O
24
–O
31
H
L
O
o
Z
L
X
OE
1
L
L
L
H
Inputs
L
X
OE
2
L
L
L
H
Inputs
CP
3
L
X
OE
3
L
L
L
H
L
X
OE
4
L
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
O
o
=
Previous O
o
before HIGH-to-LOW of CP
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2
74LVT32374 • 74LVTH32374
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
V
CC1
is associated with Bytes 1 and 2.
V
CC2
is associated with Bytes 3 and 4.
Note:
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
3
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74LVT32374 • 74LVTH32374
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
O
>
V
CC
Output at HIGH State
Output at LOW State
V
mA
mA
mA
mA
mA
−
0.5 to
+
4.6
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
50
−
50
64
128
±
64
±
128
−
65 to
+
150
°
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
−
32
64
−
40
0
85
10
°
C
ns/V
∆
t/
∆
V
Note 3:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
(Note 5)
I
I(OD)
(Note 5)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.0
Bushold Input Minimum Drive
3.0
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
µA
µA
µA
µA
µA
µA
V
CC
−
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
µA
µA
V
V
2.0
0.8
T
A
= −40°C
to
+85°C
Min
Max
−1.2
Units
V
V
V
Conditions
I
I
= −18
mA
V
O
≤
0.1V or
V
O
≥
V
CC
−
0.1V
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −32
mA
I
OL
=
100
µA
I
OL
=
24 mA
I
OL
=
16 mA
I
OL
=
32 mA
I
OL
=
64 mA
V
I
=
0.8V
V
I
=
2.0V
(Note 6)
(Note 7)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V
V
I
=
GND or V
CC
V
O
=
0.5V
V
O
=
3.0V
V
CC
<
V
O
≤
5.5V
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4
74LVT32374 • 74LVTH32374
DC Electrical Characteristics
Symbol
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Parameter
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
(Continued)
V
CC
(V)
T
A
= −40°C
to
+85°C
Min
Max
0.19
5
0.19
0.19
mA
mA
mA
mA
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
−
0.6V
Other Inputs at V
CC
or GND
Units
Conditions
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
3.6
3.6
3.6
3.6
Increase in Power Supply Current (V
CC1
or V
CC2
)
(Note 8)
3.6
0.2
mA
Note 5:
Applies to bushold version only (74LVTH32374).
Note 6:
An external driver must sink at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
Min
(Note 9)
T
A
=
25°C
Typ
0.8
−0.8
Max
Units
V
V
Conditions
C
L
=
50 pF, R
L
=
500Ω
(Note 10)
(Note 10)
Note 9:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
C
L
=
50 pF, R
L
=
500Ω
Symbol
Parameter
V
CC
=
3.3V
±
0.3V
Min
f
MAX
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
Setup Time
Hold Time
Pulse Width
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
160
1.9
1.6
1.3
1.0
1.5
2.0
1.8
0.8
3.0
4.3
4.5
4.4
4.5
4.6
5.0
Max
160
1.9
1.6
1.3
1.0
1.5
2.0
2.0
0.1
3.0
4.6
5.2
5.0
5.4
4.8
5.4
V
CC
=
2.7V
Min
Max
MHz
ns
ns
ns
ns
ns
ns
Units
Capacitance
(Note 11)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
CC
=
OPEN, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Typical
4
8
Units
pF
pF
Note 11:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
5
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