®
Final Specification
Alliance Semiconductor
P2781/82/84
General Purpose EMI Reduction IC
FEATURES
•
•
•
•
•
•
Provides up to 15 dB of EMI suppression
FCC approved method of EMI attenuation
Generates a 1X, 2X, and 4X low EMI spread
spectrum clock of the input frequency
Input frequency range from 3 to 78 MHz
External loop filter for spread % adjustment
Spreading ranges from +/-0.25% to +/-5.0%
•
•
•
•
•
•
•
Ultra low cycle-to-cycle jitter
Zero-cycle slip
3.3V operating voltage range
10 mA output drives
TTL or CMOS compatible outputs
Ultra-low power CMOS design
Available in 8 pin SOIC and TSSOP
PRODUCT DESCRIPTION
APPLICATIONS
The P278xx is a versatile spread spectrum
frequency modulator designed specifically for
digital camera and other digital video and imaging
applications.
The
P278xx
reduces
electromagnetic interference (EMI) at the clock
source, which provides system wide reduction of
EMI of all clock dependent signals. The P278xx
allows significant system cost savings by reducing
the number of circuit board layers and shielding
that are traditionally required to pass EMI
regulations.
The P278xx uses the most efficient and optimized
modulation profile approved by the FCC.
The P278xx modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized
clock and, more importantly, decreases the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by oscillators
and most frequency generators. Lowering EMI by
increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
The P278xx is targeted towards MFP, xDSL, fax
modem, set-top box, USB controller, DSC, and
embedded systems.
Figure 1 - Pin Diagram
X IN 1
XOUT 2
FS1
LF
3
4
P 2 7 8 X A -0 8 S
P 2 7 8 X A -0 8 T
8
7
6
5
VDD
FS0
M odO ut
VSS
Standard pin configuration offered in both
8 SOIC and TSSOP packages
FS0
VDD
X IN
1
2
3
P 2 7 8 X B -0 8 T
8
7
6
5
M odO ut
VSS
LF
FS1
XOUT 4
Alternative pin configuration available
only for 8 TSSOP package
Nov, 2002
Revision F
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
1 of 9
®
Final Specification
Alliance Semiconductor
Figure 2 - P278XX Block Diagram
FS 0 FS1
LF
VDD
P2781/82/84
M o d u la tio n
X IN
XO U T
F e e d b a ck
D ivid e r
C rysta l
O scilla to r
F re qu e n cy
D ivid e r
PLL
P h a se
D e te cto r
VCO
O u tp u t
D ivid e r
M odOUT
P 2 7 8 X X B lo c k D ia g ra m
VSS
PIN DESCRIPTION (P278XA)
PIN #
1
2
3
4
5
6
7
8
Name
XIN/CLKIN
XOUT
FS1
LF
VSS
ModOUT
FS0
VDD
Type
I
I
I
I
I
O
I
P
Description
Connect to crystal or clock input.
Crystal output
Digital logic input used to select input frequency range (see Table 1). This
pin has an internal pull-up resistor.
External Loop Filter for the PLL. By changing the value of the CRC circuit,
the % spread can be adjusted accordingly. See Table 2 for detail value.
Ground Connection. Connect to system ground.
Spread Spectrum Clock Output.
Digital logic input used to select input frequency range (see Table 1). This
pin has an internal pull-up resistor.
Connect to +3.3V
Table 1 - Input Frequency Selection
FS1
0
0
1
1
FS0
0
1
0
1
Input
(MHz)
3 to 9
10 to 19
20 to 38
39 to 78
Output Frequency Scaling (MHz)
P2781X
P2782X
P2784X
3 to 9
6 to 18
12 to 36
10 to 19
20 to 38
40 to 76
20 to 38
40 to 76
80 to 152
39 to 78
78 to 156
156 to 312
Modulation Rate
(KHz)
Fin / 128
Fin / 256
Fin / 512
Fin / 1024
Nov, 2002
Revision F
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
2 of 9
®
Final Specification
Alliance Semiconductor
Table 2 - Loop Filter Selection Table VDD 3.3V
R1
PIN 4 LF
C2
C1
P2781/82/84
NOTE: The BW % value is representative of typical conditions.
BW=+/-0.50%
INPUT
(MHz)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21-22
23-24
25-26
27-28
29-30
31-32
33-34
35-36
37-38
39-42
43-46
47-50
51-54
55-58
59-62
63-66
67-70
71-74
75-78
FS1 FS0 C1 (pF) C2 (pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
330,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
R1
(ohms)
220
270
390
510
620
820
1,000
330
390
510
560
620
750
820
910
1,000
1,200
330
390
510
560
620
750
820
910
1,000
1,200
330
390
510
560
620
750
820
910
1,000
1,200
BW=+/-0.75%
C1 (pF) C2 (pF)
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
330,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
R1
(ohms)
300
390
560
750
1,000
1,200
1,500
510
560
750
820
1,000
1,100
1,200
1,300
1,500
1,600
560
620
750
820
1,000
1,100
1,200
1,300
1,500
1,600
560
620
750
820
1,000
1,100
1,200
1,300
1,600
1,800
BW=+/-1.00%
C1 (pF) C2 (pF)
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
BW=+/-1.25%
R1
C1 (pF) C2 (pF)
R1
(ohms)
(ohms)
560
560
560
680
330
680
270
560
560
680
470
330
330
680
390
270
270
560
560
680
470
330
330
680
390
270
270
560
560
680
470
330
330
680
390
270
270
100,000
100,000
100,000
6,800
3,300
6,800
2,700
100,000
100,000
6,800
4,700
3,300
3,300
6,800
3,900
2,700
2,700
100,000
100,000
6,800
4,700
3,300
3,300
6,800
3,900
2,700
2,700
100,000
100,000
6,800
4,700
3,300
3,300
6,800
3,900
2,700
2,700
510
680
910
1,200
1,200
2,200
2,200
910
1,100
1,200
1,200
1,200
1,500
2,200
2,200
2,200
2,700
910
1,100
1,200
1,200
1,200
1,500
2,200
2,200
2,200
2,700
910
1,100
1,200
1,200
1,200
1,500
2,200
2,200
2,200
2,700
100,000 390
100,000 560
100,000 750
10,000 1,000
5,600 1,200
12,000 2,200
5,600 2,200
100,000 750
100,000 866(1%)
10,000 1,000
12,000 1,200
5,600 1,200
3,900 1,200
12,000 2,200
10,000 2,200
5,600 2,200
3,300 2,200
100,000 750
100,000 866(1%)
10,000 1,000
12,000 1,200
6,800 1,200
3,900 1,200
12,000 2,200
10,000 2,200
5,600 2,200
3,300 2,200
100,000 750
100,000 866(1%)
10,000 1,000
12,000 1,200
6,800 1,200
3,900 1,200
12,000 2,200
8,200 2,200
5,600 2,200
3,300 2,200
*Please contact factory
for loop filter values not listed in the above table
(info@pulsecore.com; or Ext. 17 or 25)
Nov, 2002
Revision F
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
3 of 9
®
Final Specification
Alliance Semiconductor
P2781/82/84
SPREAD SPECTRUM SELECTION
The P278xA performs Zero Cycle Slip when sets at low % spreading. This allows no occurrence of system
timing error. The optimal setting should minimize system EMI to the fullest without affecting system
performance. The spreading is described as a percentage deviation of the center frequency (Note: the center
frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example:
The P2781A is designed for PC peripheral, networking, notebook PC, and LCD monitor
applications. It is optimized for operation between 3 to 78 MHz range. The P2781A’s spread % selection is
determined by the external LF value specified in Table 2. Table 1 specifies the input frequency range. The
external LF allows the user to fine tuning the spread % to optimize the EMI reduction benefits of the spread
spectrum.
Figure 3 - P278xA Application Schematic
16MHz
1
2
3
820 Ohm
CLKIN
XOUT
FS1
LF
P2781A
VDD
FS0
ModOUT
VSS
8
0.1uF
7
+3.3V
6
5
4
0 Ohm
Modulated 16MHz with
+/-0.5% BW to target
chip
R1
C2
100,000 pF
C1
560pF
Note:
Both logic input pins FS1 and FS0 have to be connected to either VDD or VSS by a low impedance
connection such as a printed circuit board trace or zero ohms resistor. Do not leave them floating.
Nov, 2002
Revision F
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
4 of 9
®
Final Specification
Alliance Semiconductor
EMC SOFTWARE SIMULATION
By using PulseCore Semiconductor, Inc.’s proprietary EMC simulation software –
EMI-lator
, radiated system
level EMI analysis can be made easier to allow a quantitative assessment on PulseCore’s EMI reduction
products. The simulation engine of this EMC software has already been characterized to correlate with the
electrical characteristics of PulseCore EMI reduction IC’s.
Figure 4
below is an example of the simulation
result. Please visit our web site at
www.pulsecore.com
for information on how to obtain a free copy and
®
demonstration of
EMI-lator
.
Figure 4 - Simulation Result from
EMI-lator
®
®
P2781/82/84
Nov, 2002
Revision F
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
5 of 9