®
74VHC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC373M
74VHC373T
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/10
74VHC373
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
75
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (see note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
Valu e
2.0 to 5.5
0 to 5.5
0 to V
CC
-40 to +85
0 to 100
0 to 20
Unit
V
V
V
o
C
ns/V
ns/V
1) V
IN
from 30% to70%of V
CC
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
V
CC
(V)
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
2.0
3.0 to 5.5
2.0
3.0 to 5.5
2.0
3.0
4.5
3.0
4.5
V
OL
Low Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
OZ
High Impedance
Output Leakage
Current
Input Leakage Current
Quiescent Supply
Current
5.5
0 to 5.5
5.5
I
O
=-50
µ
A
I
O
=-50
µ
A
I
O
=-50
µA
I
O
=-4 mA
I
O
=-8 mA
I
O
=50
µA
I
O
=50
µ
A
I
O
=50
µA
I
O
=4 mA
I
O
=8 mA
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= 5.5V or GND
V
I
= V
CC
or GND
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.25
2.0
3.0
4.5
o
Value
T
A
= 25 C
Min.
1.5
0.7V
CC
0.5
0.3V
CC
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.44
0.44
±2.5
Typ .
Max.
-40 to 85 C
Min .
1.5
0.7V
CC
0.5
0.3V
CC
Max.
o
Un it
V
V
V
V
µA
I
I
I
CC
±
0.1
4
±
1.0
40
µ
A
µ
A
3/10
74VHC373
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co ndition
V
CC
C
L
(V)
(pF )
3.3
(*)
3.3
5.0
(**)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
5.0
(**)
3.3
3.3
(*)
5.0
(**)
5.0
(**)
3.3
(*)
5.0
3.3
(*)
5.0
(**)
(*)
(**)
(*)
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
15
50
15
50
15
50
15
50
15
50
15
50
50
50
R
L
R
L
R
L
R
L
R
L
= 1KΩ
= 1KΩ
= 1KΩ
= 1KΩ
= 1K
Ω
Value
T
A
= 25 C
Min. Typ . Max.
7.0
11.0
o
Un it
-40 to 85 C
Min . Max.
1.0
13.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
16.5
8.5
10.5
13.5
17.0
8.5
10.5
13.5
17.0
9.5
11.5
15.0
10.5
5.0
5.0
4.0
4.0
1.0
1.0
1.5
1.0
ns
ns
o
t
PLH
t
PHL
Propagation Delay
Time
D to Q
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
14.5
7.2
9.2
11.4
14.9
7.2
9.2
11.4
14.9
8.1
10.1
13.2
9.2
5.0
5.0
4.0
4.0
1.0
1.0
ns
t
PZL
t
PZH
Output EnableTime
t
PLZ
t
PHZ
t
w
t
s
t
h
t
OSLH
t
OSHL
Output Disable Time
Pulse Width (LE)
HIGH
Setup Time D to LE
HIGH or LOW
Hold Time D toLE
HIGH or LOW
Output to Output Skew
Time (note 1)
R
L
= 1KΩ
ns
ns
ns
ns
ns
(**)
3.3
(*)
5.0
(**)
3.3
5.0
(**)
3.3
(*)
5.0
(**)
50
50
(*)
1.5
1.0
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5V
±
0.5V
Note 1: Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
o
Value
T
A
= 25 C
Min.
Typ .
4
6
27
Max.
10
-40 to 85 C
Min .
Max.
10
o
Un it
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
pF
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
/8 (per Latch)
4/10
74VHC373
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
V
CC
(V)
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
5.0
-0.9
5.0
5.0
C
L
= 50 pF
3.5
1.5
o
Value
T
A
= 25 C
Min.
Typ .
0.6
-0.6
Max.
0.9
-40 to 85 C
Min .
Max.
o
Un it
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (V
ILD
), 0V to threshold (V
IHD
), f=1MHz.
TEST CIRCUIT
T EST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 1KΩ orequivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
SW IT CH
Open
V
CC
GND
5/10
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