74VHCT00A datasheet, PDF - EEWORLD Datasheet

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74VHCT00A: DescriptionQuad 2-Input NAND Gate; File Size126KB，8 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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74VHCT00A Overview

Quad 2-Input NAND Gate

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74VHCT00A Quad 2-Input NAND Gate

July 1997

Revised February 2005

74VHCT00A

Quad 2-Input NAND Gate

General Description

The VHCT00A is an advanced high-speed CMOS 2-Input

NAND Gate fabricated with silicon gate CMOS technology.

It achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The internal circuit is composed of 3

stages, including buffer output, which provide high noise

immunity and stable output.

Protection circuits ensure that 0V to 7V can be applied to

the input pins without regard to the supply voltage and to

the output pins with V

0V. These circuits prevent

device destruction due to mismatched supply and input/

output voltages. This device can be used to interface 3V to

5V systems and two supply systems such as battery

backup.

Features

■

High speed: t

5.0 ns (typ) at T

2.0V, V

0.8V

■

High noise immunity: V

■

Power down protection is provided on all inputs and

outputs

■

Low noise: V

OLP

0.8V (max)

■

Low power dissipation:

A (max) at T

■

Pin and function compatible with 74HCT00

Ordering Code:

Order Number

74VHCT00AM

74VHCT00ASJ

74VHCT00AMTC

74VHCT00AMTCX_NL

(Note 1)

74VHCT00AN

74VHCT00AN_NL

(Note 1)

Package

Number

M14A

M14D

MTC14

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.

DS500023

www.fairchildsemi.com

74VHCT00A Related Products

	74VHCT00A	74VHCT00AMTC	74VHCT00AN	74VHCT00AMTCX_NL	74VHCT00AN_NL
Description	Quad 2-Input NAND Gate	Quad 2-Input NAND Gate	Quad 2-Input NAND Gate	Quad 2-Input NAND Gate	Quad 2-Input NAND Gate
Is it Rohs certified?	-	conform to	conform to	conform to	conform to
Maker	-	Fairchild	Fairchild	Fairchild	Fairchild
Parts packaging code	-	TSSOP	DIP	TSSOP	DIP
package instruction	-	TSSOP, TSSOP14,.25	DIP, DIP14,.3	TSSOP, TSSOP14,.25	DIP, DIP14,.3
Contacts	-	14	14	14	14
Reach Compliance Code	-	compli	compli	compli	compli
series	-	AHCT/VHCT	AHCT/VHCT	AHCT/VHCT	AHCT/VHCT
JESD-30 code	-	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14	R-PDIP-T14
length	-	5 mm	19.18 mm	5 mm	19.18 mm
Load capacitance (CL)	-	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	-	NAND GATE	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	-	0.008 A	0.008 A	0.008 A	0.008 A
Number of functions	-	4	4	4	4
Number of entries	-	2	2	2	2
Number of terminals	-	14	14	14	14
Maximum operating temperature	-	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	TSSOP	DIP	TSSOP	DIP
Encapsulate equivalent code	-	TSSOP14,.25	DIP14,.3	TSSOP14,.25	DIP14,.3
Package shape	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE
method of packing	-	RAIL	RAIL	TAPE AND REEL	RAIL
Peak Reflow Temperature (Celsius)	-	260	NOT SPECIFIED	260	NOT SPECIFIED
power supply	-	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Su	-	9 ns	9 ns	9 ns	9 ns
propagation delay (tpd)	-	9 ns	9 ns	9 ns	9 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	-	NO	NO	NO	NO
Maximum seat height	-	1.2 mm	5.08 mm	1.2 mm	5.08 mm
Maximum supply voltage (Vsup)	-	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	-	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	-	5 V	5 V	5 V	5 V
surface mount	-	YES	NO	YES	NO
technology	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	-	GULL WING	THROUGH-HOLE	GULL WING	THROUGH-HOLE
Terminal pitch	-	0.65 mm	2.54 mm	0.65 mm	2.54 mm
Terminal location	-	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	-	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	-	4.4 mm	7.62 mm	4.4 mm	7.62 mm

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