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74VHCT00AN

Description
Quad 2-Input NAND Gate
Categorylogic    logic   
File Size126KB,8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74VHCT00AN Overview

Quad 2-Input NAND Gate

74VHCT00AN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codecompli
seriesAHCT/VHCT
JESD-30 codeR-PDIP-T14
length19.18 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingRAIL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Prop。Delay @ Nom-Su9 ns
propagation delay (tpd)9 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
74VHCT00A Quad 2-Input NAND Gate
July 1997
Revised February 2005
74VHCT00A
Quad 2-Input NAND Gate
General Description
The VHCT00A is an advanced high-speed CMOS 2-Input
NAND Gate fabricated with silicon gate CMOS technology.
It achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer output, which provide high noise
immunity and stable output.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
High speed: t
PD
5.0 ns (typ) at T
A
2.0V, V
IL
25
q
C
0.8V
High noise immunity: V
IH
Power down protection is provided on all inputs and
outputs
Low noise: V
OLP
0.8V (max)
25
q
C
Low power dissipation:
I
CC
2
P
A (max) at T
A
Pin and function compatible with 74HCT00
Ordering Code:
Order Number
74VHCT00AM
74VHCT00ASJ
74VHCT00AMTC
74VHCT00AMTCX_NL
(Note 1)
74VHCT00AN
74VHCT00AN_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
N14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.
© 2005 Fairchild Semiconductor Corporation
DS500023
www.fairchildsemi.com

74VHCT00AN Related Products

74VHCT00AN 74VHCT00A 74VHCT00AMTC 74VHCT00AMTCX_NL 74VHCT00AN_NL
Description Quad 2-Input NAND Gate Quad 2-Input NAND Gate Quad 2-Input NAND Gate Quad 2-Input NAND Gate Quad 2-Input NAND Gate
Is it Rohs certified? conform to - conform to conform to conform to
Maker Fairchild - Fairchild Fairchild Fairchild
Parts packaging code DIP - TSSOP TSSOP DIP
package instruction DIP, DIP14,.3 - TSSOP, TSSOP14,.25 TSSOP, TSSOP14,.25 DIP, DIP14,.3
Contacts 14 - 14 14 14
Reach Compliance Code compli - compli compli compli
series AHCT/VHCT - AHCT/VHCT AHCT/VHCT AHCT/VHCT
JESD-30 code R-PDIP-T14 - R-PDSO-G14 R-PDSO-G14 R-PDIP-T14
length 19.18 mm - 5 mm 5 mm 19.18 mm
Load capacitance (CL) 50 pF - 50 pF 50 pF 50 pF
Logic integrated circuit type NAND GATE - NAND GATE NAND GATE NAND GATE
MaximumI(ol) 0.008 A - 0.008 A 0.008 A 0.008 A
Number of functions 4 - 4 4 4
Number of entries 2 - 2 2 2
Number of terminals 14 - 14 14 14
Maximum operating temperature 85 °C - 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C - -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP - TSSOP TSSOP DIP
Encapsulate equivalent code DIP14,.3 - TSSOP14,.25 TSSOP14,.25 DIP14,.3
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH IN-LINE
method of packing RAIL - RAIL TAPE AND REEL RAIL
Peak Reflow Temperature (Celsius) NOT SPECIFIED - 260 260 NOT SPECIFIED
power supply 5 V - 5 V 5 V 5 V
Prop。Delay @ Nom-Su 9 ns - 9 ns 9 ns 9 ns
propagation delay (tpd) 9 ns - 9 ns 9 ns 9 ns
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified
Schmitt trigger NO - NO NO NO
Maximum seat height 5.08 mm - 1.2 mm 1.2 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V 5 V 5 V
surface mount NO - YES YES NO
technology CMOS - CMOS CMOS CMOS
Temperature level INDUSTRIAL - INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form THROUGH-HOLE - GULL WING GULL WING THROUGH-HOLE
Terminal pitch 2.54 mm - 0.65 mm 0.65 mm 2.54 mm
Terminal location DUAL - DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - 30 NOT SPECIFIED NOT SPECIFIED
width 7.62 mm - 4.4 mm 4.4 mm 7.62 mm
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