M65656G
32 K
8 Very Low Power CMOS SRAM Rad Tolerant
Introduction
The M65656G is a very low power CMOS static RAM
organized as 32768
×
8 bits.
TEMIC brings the solution for applications where fast
computing is as mandatory as low consumption, such as
aerospace electronics, portable instruments or embarked
systems.
Using an array of six transistors (6T) memory cells, the
M65656G combines an extremely low standby supply
current (Typical value = 0.1
µA)
with a fast access time
at 40 ns. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
Extra protection against heavy ions is given by the use of
an epitaxial layer of a P substrate.
The M65656G is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S), ESA
SCC 9000 and QML.
Features
D
Access time
40, 55 ns
D
Very low power consumption
active : 50 mW (typ)
standby : 0.5
µ
W (typ)
data retention : 0.4
µ
W (typ)
D
D
D
D
D
D
D
Wide temperature range : –55 to + 125°C
300 and 600 mils width package
TTL compatible inputs and outputs
Asynchronous
Single 5 volt supply
Equal cycle and access time
Gated inputs : no pull-up/down
resistors are required
Interface
Block Diagram
Rev. F – June 5,2000
1
M65656G
Pin Configuration
Side Brazed 300 mils 28 pins
Multilayer Flat Pack 28 pins 400 mils
(Top View)
Pin Names
A
0
-A
14
:
I/O0-I/O7 :
V
CC
:
GND :
Address inputs
Input/Output
Power
Ground
CS :
W:
OE :
Chip-Select
Write Enable
Output Enable
Truth Table
CS
H
L
L
L
W
X
H
L
H
OE
X
L
X
H
INPUTS/
OUTPUTS
Z
DATA OUT
DATA IN
Z
MODE
Deselect/
POWER-DOWN
Read
Write
Output Disable
L = low, H = high, X = H or L, Z = high impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . -0.3 V to + 7.0 V
Input or Output voltage applied : . . . . . (Gnd – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65
o
C to + 150
o
C
Electro static discharge voltage . . . . . . . . . . > 2000 V (MIL STD 883,
METHOD 3015)
Operating Range
OPERATING VOLTAGE
Military
V
CC
= 5 V
±
10 %
OPERATING TEMPERATURE
– 55
_C
to + 125
_C
DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH(1)
Note :
(1)
Ground
Input low voltage
input high voltage
DESCRIPTION
Supply voltage
MINIMUM
4.5
0.0
– 0.3
2.2
TYPICAL
5.0
0.0
0.0
–
MAXIMUM
5.5
0.0
0.8
Vcc + 0.3
UNIT
V
V
V
V
1. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1.0 pulse 50 ns.
2
Rev. F – June 5,2000
M65656G
Capacitance
PARAMETER
Cin
Cout
Note :
(2)
(2)
DESCRIPTION
Input capacitance
Output capacitance
MINIMUM
–
–
TYPICAL
–
–
MAXIMUM
8
12
UNIT
pF
pF
2. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
DC Parameter
PARAMETER
IIX
IOZ (3)
VOL
VOH
Notes :
(4)
(4)
(3)
DESCRIPTION
Input leakage current
Output leakage current
Output low voltage
Output high voltage
MINIMUM
– 1.0
– 1.0
–
2.4
TYPICAL
–
–
–
–
MAXIMUM
1.0
1.0
0.4
–
UNIT
µA
µA
V
V
3. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
4. Vcc min, IOL = 4 mA, IOH = –1.0 mA.
Consumption
SYMBOL
ICCSB (5)
ICCSB1 (6)
ICCOP (7)
Notes :
PARAMETER
Standby supply current
Standby supply current
Operating supply current
M65656G
V – 45
5
100
85
M65656G
V – 55
5
100
85
UNIT
mA
µA
mA
VALUE
max
max
max
5. CS
≥
VIH, Vin
≥
VIH or Vin
≤
VIL.
6. CS
≥
Vcc – 0.3 V, Iout = 0 mA. Vin
≥
Vcc – 0.3 V or Vin
≤
0.3 V.
7. Vcc max, Iout = 0 mA, Vin = Gnd/Vcc. Duty cycle 100 %, F = 5 MHz, derating = 12 mA/MHz.
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1. Chip select (CS) must be held high during data
retention ; within Vcc to Vcc – 0.2 V.
2. Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power
dissipation.
3. CS must be kept between Vcc -0.3 V and 70 % of Vcc
during the power up and power down transitions.
4. The RAM can begIn operation > TR after Vcc
reaches the minimum operating voltage (4.5 V).
Timing
Rev. F – June 5,2000
3
M65656G
Data Retention Characteristics
PARAMETER
VCCDR
TCDR
TR
ICCDR1 (10)
ICCDR2 (10)
DESCRIPTION
Vcc for data retention
Chip deselect to data retention time
Operation recovery time
Data retention current
@ 2.0 V : M-65656GV
Data retention current
@ 3.0 V : M-65656GV
MINIMUM
2.0
0.0
TAVAV (9)
TYPICAL (8)
–
–
–
0.1
0.3
MAXIMUM
–
–
–
80
90
UNIT
V
ns
ns
µA
µA
Notes :
8. TA = 25°C.
9. TAVAV = Read cycle time.
10. CS = Vcc, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
4
Rev. F – June 5,2000
M65656G
AC Parameters
AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output load : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See fig. 1a, 1b
Write Cycle
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ (11)
TWLWH
TWHAX
TWHDX
TWHQX (11)
PARAMETER
Write cycle time
Address set-up time
Address valid to end of write
Data set-up time
CS low to write end
Write low to high Z
Write pulse width
Address hold to end of write
Data hold time
Write high to low Z
M65656G
– 40
40
0
30
22
30
15
30
0
0
0
M65656G
– 55
55
0
40
25
40
20
40
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
Notes :
11. Specified with C
L
= 5 pF (see figure 1b). Guaranteed but not tested.
Rev. F – June 5,2000
5
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