AS7C33256PFS36A-100TQCN datasheet, PDF

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AS7C33256PFS36A-100TQCN: DescriptionStandard SRAM, 256KX36, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100; Categorystorage storage; File Size455KB，16 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]; Environmental Compliance

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AS7C33256PFS36A-100TQCN Overview

Standard SRAM, 256KX36, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33256PFS36A-100TQCN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	12 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3/e6
length	20 mm
memory density	9437184 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.325 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	PURE MATTE TIN/TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
Base Number Matches	1

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April 2004

AS7C33256PFS32A

AS7C33256PFS36A

3.3V 256K

32/36 pipelined burst synchronous SRAM

Features

Organization: 262,144 words x 32 or 36 bits

Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Fast OE access time: 3.5/3.8/4.0/5.0 ns

Fully synchronous register-to-register operation

Single register “Flow-through” option

Single-cycle deselect

Dual-cycle deselect also available (AS7C33512PFD18A,

AS7C33256PFD32A/AS7C33256PFD36A)

• Asynchronous output enable control

• Available in100-pin TQFP

•

Byte write enables

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

30 mW typical standby power in power down mode

NTD™

pipeline architecture available ( AS7C33512NTD18A,

AS7C33256NTD32A/ AS7C33256NTD36A)

1 NTD™ is a trademark of Alliance Semiconductor Corporation.

All trademarks mentioned in this document are the property of their respective

owners.

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[17:0]

Burst logic

18 2 16

Address

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

CLR

2 18

256K × 32/36

Memory

array

BWE

GWE

36/32

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

36/32

DQ[a:d]

Selection guide

–166

Minimum cycle time

Maximum pipelined clock frequency

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current

4/16/04, v.3.0

–150

6.6

150

3.8

450

110

–133

7.5

133

425

100

–100

100

325

Units

MHz

P. 1 of 16

166

3.5

475

130

Alliance Semiconductor

AS7C33256PFS32A

AS7C33256PFS36A

Functional description

The AS7C33256PFS32A and AS7C33256PFS36A are high-performance CMOS 8-Mbit synchronous Static Random Access

Memory (SRAM) devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline

for highest frequency on any given technology.

Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t

) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus

frequencies. Two-chip enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst

operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The

burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.

In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled LOW, and both address strobes are HIGH. Burst mode is selectable with the

LBO

input. With

LBO

unconnected or driven HIGH, burst operations use an interleaved count sequence. With

LBO

driven LOW, the

device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in

single cycle deselect features during real cycle.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP follow.

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC LOW (and

ADSP

HIGH).

• Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C33256PFS32A and AS7C33256PFS36A family operates from a core 3.3V power supply. I/Os use a separate power

supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

TQFP thermal Capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

I/O

Test conditions

= 0V

= V

OUT

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

4–layer

Symbol

Typical

Units

°C/W

4/16/04, v.3.0

Alliance Semiconductor

P. 3 of 16

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Description	Standard SRAM, 256KX36, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX36, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX36, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX36, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	Standard SRAM, 256KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87
Contacts	100	100	100	100	100	100	100	100
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	12 ns	12 ns	12 ns	10 ns	10 ns	12 ns	10 ns	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e3/e6	e3/e6	e3/e6	e3/e6	e3/e6	e3/e6	e3/e6	e3/e6
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
memory density	9437184 bit	8388608 bit	9437184 bit	9437184 bit	9437184 bit	8388608 bit	8388608 bit	8388608 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	36	32	36	36	36	32	32	32
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	100	100	100	100	100	100	100	100
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	85 °C	85 °C	85 °C	70 °C
organize	256KX36	256KX32	256KX36	256KX36	256KX36	256KX32	256KX32	256KX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260
power supply	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum standby current	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.325 mA	0.325 mA	0.325 mA	0.45 mA	0.45 mA	0.325 mA	0.45 mA	0.45 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH	PURE MATTE TIN/TIN BISMUTH
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	40	40	40	40	40	40	40
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Maker	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	-	-	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]

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