80C286/883
March 1997
High Performance Microprocessor with Memory
Management and Protection
Description
The Intersil 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 2
24
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with existing 80C86 and 80C88 software. In protected
virtual address mode, the 80C286/883 is source code com-
patible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
Ordering Information
PACKAGE
68 Pin PGA
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
10MHz
-
IG80C286-10
12.5MHz
CG80C286-12
IG80C286-12
16MHz
CG80C286-16
-
-
-
20MHz
CG80C286-20
-
-
-
25MHz
-
-
-
-
PKG. NO.
G68.B
G68.B
G68.B
G68.B
-55
o
C to +125
o
C MG80C286-10/883 MG80C286-12/883
5962-9067801MXC 5962-9067802MXC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2948.1
3-128
80C286/883
Pinout
68 LEAD PGA, COMPONENT PAD VIEW
As viewed from underside of the component when mounted on the board.
D10
D11
D12
D13
D14
49
50
D7
D0
D1
D2
D3
D4
D5
35
A0
A2
V
CC
A3
A5
A7
A9
A11
A13
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
34
32
30
28
26
24
22
20
18
36
33
31
29
27
25
23
21
19
17
A12
37
38
39
40
41
42
43
44
45
46
47
48
D6
51
53
55
57
59
61
63
65
67
52
54
56
58
60
62
64
66
68
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/INTA
LOCK
16
15
A15
14
13
A17
12
11
A19
10
9
A21
8
7
A22
6
5
PEACK
4
3
S1
NC
ERROR
2
1
D15
V
SS
D8
D9
PIN 1 INDICATOR
P.C. BOARD VIEW
As viewed from the component side of the P.C. board.
D15
D14
D13
D12
D11
D10
V
SS
35
36
33
31
29
27
25
23
21
4
3
S1
6
5
PEACK
8
7
A22
10
9
A21
12
11
A19
14
13
A17
16
15
A15
19
17
A12
34
32
30
28
26
24
22
20
18
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
A0
A2
V
CC
A3
A5
A7
A9
A11
A13
A14
D0
D9
D2
39
40
A18
D8
A16
D1
37
38
ERROR
D7
D6
D5
BHE
D4
43
44
V
SS
A14
A16
A18
A20
A23
V
SS
NC
S0
51
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/INTA
LOCK
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
52
54
56
58
60
62
64
66
68
53
55
57
59
61
63
65
67
2
1
NC
49
50
47
48
45
46
PIN 1 INDICATOR
NC
BHE
S0
3-129
A23
A20
D3
41
42
80C286/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied. . . . . . GND -1.0V to V
CC
+1.0V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θ
JA
θ
JC
o
C/W
o
C/W
PGA Package . . . . . . . . . . . . . . . . . . . . .
35
6
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)
System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)
Input RISE and FALL Time (From 0.8V to 2.0V
80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUB-
GROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
MIN
-0.5
2.0
-0.5
3.6
-
3.0
V
CC
-0.4
1, 2, 3
-10
MAX
0.8
V
CC
+0.5
1.0
V
CC
+0.5
0.4
-
-
10
UNITS
V
V
V
V
V
V
V
µA
PARAMETER
Input LOW Voltage
Input HIGH Voltage
CLK Input LOW Voltage
CLK Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
SYMBOL
V
IL
V
IH
V
ILC
V
IHC
V
OL
V
OH
CONDITIONS
V
CC
= 4.5V
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
I
OL
= 2.0mA, V
CC
= 4.5V
I
OH
= -2.0mA, V
CC
= 4.5V
I
OH
= -100µA, V
CC
= 4.5V
Input Leakage Current
I
I
V
IN
= GND or V
CC
,
V
CC
= 5.5V,
Pins 29, 31, 57, 59, 61,
63-64
V
CC
= 4.5V and 5.5V,
V
IN
= 1.0V, Note 1
V
CC
= 4.5V and 5.5V,
V
IN
= 3.0V, Note 2
V
CC
= 4.5V and 5.5V
V
IN
= GND, Note 5
V
O
= GND or V
CC
V
CC
= 5.5V,
Pins 1, 7-8, 10-28, 32-34
80C286-10/883, Note 4
80C286-12/883, Note 4
Input Sustaining Current
LOW
Input Sustaining Current
HIGH
Input Sustaining Current
on BUSY and ERROR
Pins
Output Leakage Current
I
BHL
I
BHH
I
SH
1, 2, 3
1, 2, 3
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
38
-50
-30
200
-400
-500
µA
µA
µA
I
O
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-10
10
µA
Active Power Supply
Current
Standby Power
Supply Current
NOTES:
I
CCOP
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-
-
185
220
5
mA
mA
mA
I
CCSB
V
CC
= 5.5V, Note 3
1, 2, 3
-
2. I
BHL
should be measured after lowering V
IN
to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
3. I
BHH
should be measured after raising V
IN
to V
CC
and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
4. I
CCSB
should be tested with the clock stopped in phase two of the processor clock cycle. V
IN
= V
CC
or GND, V
CC
= 5.5V, outputs unloaded.
5. I
CCOP
measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. V
IN
= 2.4V or 0.4V, V
CC
= 5.5V, outputs unloaded.
6. I
SH
should be measured after raising V
IN
to V
CC
and then lowering to 0V on pins 53 and 54.
3-130
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz
PARAMETER
System Clock
(CLK) Period
System Clock
(CLK) Low Time
System Clock (CLK)
High Time
Asynchronous Inputs
SETUP Time
(Note 1)
Asynchronous Inputs
HOLD Time
(Note 1)
RESET SETUP Time
SYMBOL
1
CONDITIONS
V
CC
= 4.5V and 5.5V
GROUP A
SUBGROUPS
9, 10, 11
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
MIN
50
MAX
-
12.5MHz
MIN
40
MAX
-
UNITS
ns
2
V
CC
= 4.5V and 5.5V
at 1.0V
V
CC
= 4.5V and 5.5V
at 3.6V
V
CC
= 4.5V
and 5.5V
9, 10, 11
12
-
11
-
ns
3
9, 10, 11
16
-
13
-
ns
4
9, 10, 11
20
-
15
-
ns
5
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
20
-
15
-
ns
6
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V
and 5.5V
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
19
-
10
-
ns
RESET HOLD Time
7
9, 10, 11
0
-
0
-
ns
Read Data
SETUP Time
Read Data
HOLD Time
READY SETUP Time
8
9, 10, 11
8
-
5
-
ns
9
9, 10, 11
4
-
4
-
ns
10
9, 10, 11
26
-
20
-
ns
READY HOLD Time
11
9, 10, 11
25
-
20
-
ns
Status/PEACK Active
Delay, (Note 4)
12A
9, 10, 11
1
22
1
21
ns
Status/PEACK
Inactive Delay
(Note 3)
Address Valid
Delay (Note 2)
12B
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
1
30
1
24
ns
13
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
1
35
1
32
ns
Write Data
Valid Delay, (Note 2)
14
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
40
0
31
ns
3-131
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz
PARAMETER
HLDA Valid Delay
(Note 5)
SYMBOL
15
CONDITIONS
V
CC
= 4.5V and
5.5V, C
L
= 100pF
IL = |2mA|
GROUP A
SUBGROUPS
9, 10, 11
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
MIN
0
MAX
47
12.5MHz
MIN
0
MAX
25
UNITS
ns
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
80C286/883
10MHz
PARAMETER
CLK Input Capacitance
Other Input Capacitance
I/O Capacitance
Address/Status/Data
Float Delay
Address Valid to Status
SETUP Time
NOTES:
1. Output Load: C
L
= 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. I
L
= -6mA (V
OH
to Float), I
L
= 8mA (V
OL
to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Group C & D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
SYMBOL
C
CLK
C
IN
C
I/O
15
19
I
L
= | 2.0mA|
CONDITIONS
FREQ = 1MHz
FREQ = 1MH
FREQ = 1MH
NOTES
5
5
5
1, 3, 4, 5
1, 2, 5
TEMPERATURE
T
A
= +25
o
C
T
A
= +25
o
C
T
A
= +25
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
MIN
-
-
-
0
27
MAX
10
10
10
47
-
12.5MHz
MIN
-
-
-
0
20
MAX
10
10
10
32
-
UNITS
pF
pF
pF
ns
ns
3-132
Embedded System
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