EPM570GM256A5N datasheet, PDF - EEWORLD Datasheet

EPM570GM256A5N: DescriptionFlash PLD, 8.7ns, 440-Cell, CMOS, PBGA256, LEAD FREE, MICRO, FBGA-256; CategoryProgrammable logic devices Programmable logic; File Size1MB，108 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EPM570GM256A5N Overview

Flash PLD, 8.7ns, 440-Cell, CMOS, PBGA256, LEAD FREE, MICRO, FBGA-256

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA, BGA256,20X20,20
Contacts	256
Reach Compliance Code	compliant
Other features	IT CAN ALSO OPERATE AT 3.3V
In-system programmable	YES
JESD-30 code	R-PBGA-B256
JESD-609 code	e1
JTAG BST	YES
Dedicated input times
Number of I/O lines	160
Number of macro cells	440
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 160 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA256,20X20,20
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1.5/3.3,1.8 V
Programmable logic type	FLASH PLD
propagation delay	8.7 ns
Certification status	Not Qualified
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
Base Number Matches	1

Section I. MAX II Device

Family Data Sheet

This section provides designers with the data sheet specifications for

MAX

II devices. The chapters contain feature definitions of the internal

architecture, Joint Test Action Group (JTAG) and in-system

programmability (ISP) information, DC operating conditions, AC timing

parameters, and ordering information for MAX II devices.

This section includes the following chapters:

■

Chapter 1. Introduction

Chapter 2. MAX II Architecture

Chapter 3. JTAG and In-System Programmability

Chapter 4. Hot Socketing and Power-On Reset in MAX II Devices

Chapter 5. DC and Switching Characteristics

Chapter 6. Reference and Ordering Information

Revision History

Refer to each chapter for its own specific revision history. For information

about when each chapter was updated, refer to the Chapter Revision

Dates section, which appears in the complete handbook.

Altera Corporation

Section I–1

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