HY27SH084G2M-TCB datasheet, PDF

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HY27SH084G2M-TCB: DescriptionFlash, 512MX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48; Categorystorage storage; File Size416KB，47 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY27SH084G2M-TCB Overview

Flash, 512MX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48

HY27SH084G2M-TCB Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	TSOP1
package instruction	TSOP1, TSSOP48,.8,20
Contacts	48
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	30 ns
Other features	CONTAINS ADDITIONAL 512M BIT SPARE MEMORY
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	18.4 mm
memory density	4294967296 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	4K
Number of terminals	48
word count	536870912 words
character code	512000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
page size	2K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	128K
Maximum standby current	0.0002 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	NAND TYPE
width	12 mm
Base Number Matches	1

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HY27UH(08/16)4G2M Series

HY27SH(08/16)4G2M Series

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash

Document Title

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

1) Add Errata

tCLS

Specification

Relaxed value

Case

Specification

0.1

Read(all)

Except for

Relaxed value ID Read

ID Read

2) Add note.4(table14)

3) Add application note(Power on/off Sequence & Auto sleep mode)

- Texts & figures are added.

tCLH tWP tALS tALH

tRC

tDS

tWC

25us

27us

History

Initial Draft.

Draft Date

Feb. 04. 2004

Remark

Preliminary

tRP tREH tREA

feb. 07. 2005

Preliminary

1) Change AC parameters

case

Before

0.2

Afer

x16

x8, x16

tDH

Mar. 03. 2005 Preliminary

2) Add tADL(=100ns) parameters

3) Add Muliti Die Concurrent Operations and Extended Read Status

- Texts and table are added.

4) Edit Table.8

Rev 0.7 / Nov. 2005

HY27UH(08/16)4G2M Series

HY27SH(08/16)4G2M Series

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27(U/S)H(08/16)4G2M series is a 512Mx8bit with spare 8Mx8 bit capacity. The device is offered in 1.8V

Vcc Power Supply and in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 60ns cycle time per word. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP# input pin.

The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-

tiple memories the RB# pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27(U/S)H(08/16)4G2M extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the

code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-

tion.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.

The HYNIX HY27(U/S)H(08/16)4G2M series is available in 48 - TSOP1 12 x 20 mm.

1.1 Product List

PART NUMBER

HY27SH084G2M

HY27SH164G2M

HY27UH084G2M

HY27UH164G2M

ORIZATION

x16

VCC RANGE

1.70 - 1.95 Volt

48TSOP1

2.7V - 3.6 Volt

PACKAGE

Rev 0.7 / Nov. 2005

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