M82C288
BUS CONTROLLER FOR M80286 PROCESSORS
(M82C288-10 M82C288-8 M82C288-6)
Military
Y
Provides Commands and Controls for
Local and System Bus
Wide Flexibility in System
Configurations
Implemented in High Speed CHMOS III
Technology
Fully Compatible with the HMOS
M82288
Y
Y
Y
Fully Static Device
Single
a
5V Supply
Available in 20 Pin Cerdip Package
(See Packaging Spec Order
231369)
Y
Y
Y
The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The
M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and
supports a low power mode The bus controller provides command and control outputs with flexible timing
options Separate command outputs are used for memory and I O devices The data bus is controlled with
separate data enable and direction control signals
Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high
speed bus cycles
20 Pin Cerdip Package
271077 –2
Figure 2 M82C288 Pin
Configuration
271077 – 1
Figure 1 M82C288 Block Diagram
November 1991
Order Number 271077-006
M82C288
Table 1 Pin Description
The following pin function descriptions are for the M82C288 bus controller
Symbol Type
CLK
I
Name and Function
SYSTEM CLOCK
provides the basic timing control for the M82C288 in an M80286
microsystem Its frequency is twice the internal processor clock frequency The falling edge
of this input signal establishes when inputs are sampled and command and control outputs
change
BUS CYCLE STATUS
starts a bus cycle and along with M IO defines the type of bus
cycle These inputs are active LOW A bus cycle is started when either S1 or S0 is sampled
LOW at the falling edge of CLK Setup and hold times must be met for proper operation
M80286 Bus Cycle Status Definition
M IO
0
0
0
0
1
1
1
1
M IO
I
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Interrupt Acknowledge
I O Read
I O Write
None Idle
Halt or Shutdown
Memory Read
Memory Write
None Idle
Type of Bus Cycle
S0 S1
I
MEMORY OR I O SELECT
determines whether the current bus cycle is in the memory
space or I O space When LOW the current bus cycle is in the I O space Setup and hold
times must be met for proper operation
MULTIBUS MODE SELECT
determines timing of the command and control outputs When
HIGH the bus controller operates with MULTIBUS I compatible timings When LOW the
bus controller optimizes the command and control output timing for short bus cycles The
function of the CEN AEN input pin is selected by this signal This input is typically a
strapping option and not dynamically changed
COMMAND ENABLE LATCHED
is a bus controller select signal which enables the bus
controller to resopnd to the current bus cycle being initiated CENL is an active HIGH input
latched internally at the end of each T
S
cycle CENL is used to select the appropriate bus
controller for each bus cycle in a system where the CPU has more than one bus it can use
This input may be connected to V
CC
to select this M82C288 for all transfers No control
inputs affect CENL Setup and hold times must be met for proper operation
COMMAND DELAY
allows delaying the start of a command CMDLY is an active HIGH
input If sampled HIGH the command output is not activated and CMDLY is again sampled
at the next CLK cycle When sampled LOW the selected command is enabled If READY is
detected LOW before the command output is activated the M82C288 will terminate the bus
cycle even if no command was issued Setup and hold times must be satisified for proper
operation This input may be connected to GND if no delays are required before starting a
command This input has no effect on M82C288 control outputs
READY
indicates the end of the current bus cycle READY is an active LOW input
MULTIBUS I mode requires at least one wait state to allow the command outputs to
become active READY must be LOW during reset to force the M82C288 into the idle state
Setup and hold times must be met for proper operation The M82C284 drives READY LOW
during RESET
MB
I
CENL
I
CMDLY
I
READY
I
2
M82C288
Table 1 Pin Description
(Continued)
Symbol
CEN AEN
Type
I
Name and Function
COMMAND ENABLE ADDRESS ENABLE
controls the command and DEN
outputs of the bus controller CEN AEN inputs may be asynchronous to CLK
Setup and hold times are given to assure a guaranteed response to synchronous
inputs This input may be connected to V
CC
or GND
When MB is HIGH this pin has the AEN function AEN is an active LOW input which
indicates that the CPU has been granted use of a shared bus and the bus controller
command outputs may exit 3-state OFF and become inactive (HIGH) AEN HIGH
indicates that the CPU does not have control of the shared bus and forces the
command outputs into 3-state OFF and DEN inactive (LOW)
When MB is LOW this pin has the CEN function CEN is an unlatched active HIGH
input which allows the bus controller to activate its command and DEN outputs
With MB LOW CEN LOW forces the command and DEN outputs inactive but does
not tristate them
ALE
O
ADDRESS LATCH ENABLE
controls the address latches used to hold an address
stable during a bus cycle This control output is active HIGH ALE will not be issued
for the halt bus cycle and is not affected by any of the control inputs
MASTER CASCADE ENABLE
signals that a cascade address from a master
M8259A interrupt controller may be placed onto the CPU address bus for latching
by the address latches under ALE control The CPU’s address bus may then be
used to broadcast the cascade address to slave interrupt controllers so only one of
them will respond to the interrupt acknowledge cycle This control output is active
HIGH MCE is only active during interrupt acknowledge cycles and is not affected
by any control input Using MCE to enable cascade address drivers requires
latches which save the cascade address on the falling edge of ALE
DATA ENABLE
controls when data transceivers connected to the local data bus
should be enabled DEN is an active HIGH control output DEN is delayed for write
cycles in the MULTIBUS I mode
DATA TRANSMIT RECEIVE
establishes the direction of data flow to or from the
local data bus When HIGH this control output indicates that a write bus cycle is
being performed A LOW indicates a read bus cycle DEN is always inactive when
DT R changes states This output is HIGH when no bus cycle is active DT R is not
affected by any of the control inputs
I O WRITE COMMAND
instructs an I O device to read the data on the data bus
This command output is active LOW The MB and CMDLY input control when this
output becomes active READY controls when it becomes inactive
I O READ COMMAND
instructs an I O device to place data onto the data bus
This command output is active LOW The MB and CMDLY input control when this
output becomes active READY controls when it become inactive
MEMORY WRITE COMMAND
instructs a memory device to read the data on the
data bus This command output is active LOW The MB and CMDLY inputs control
when this output becomes active READY controls when it becomes inactive
MEMORY READ COMMAND
instructs the memory device to place data onto the
data bus This command output is active LOW The MB and CMDLY inputs control
when this output becomes active READY controls when it becomes inactive
MCE
O
DEN
O
DT R
O
IOWC
O
IORC
O
MWTC
O
MRDC
O
3
M82C288
Table 1 Pin Description
(Continued)
Symbol
INTA
Type
O
Name and Function
INTERRUPT ACKNOWLEDGE
tells an interrupting device that its interrupt request
is being acknowledged This command output is active LOW The MB and CMDLY
inputs control when this output becomes active READY controls when it becomes
inactive
System Power
a
5V Power Supply
System Ground
0V
Table 2 Command and Control Outputs for Each Type of Bus Cycle
Type of
Bus Cycle
Interrupt Acknowledge
I O Read
I O Write
None Idle
Halt Shutdown
Memory Read
Memory Write
None Idle
M IO
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Command
Activated
INTA
IORC
IOWC
None
None
MRDC
MWTC
None
DT R
State
LOW
LOW
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
ALE DEN
Issued
YES
YES
YES
NO
NO
YES
YES
NO
MCE
Issued
YES
NO
NO
NO
NO
NO
NO
NO
V
CC
GND
Operating Modes
Two types of buses are supported by the M82C288
MULTIBUS I and non-MULTIBUS I When the MB
input is strapped HIGH MULTIBUS I timing is used
In MULTIBUS I mode the M82C288 delays com-
mand and data activation to meet IEEE-796 require-
ments on address to command active and write data
to command active setup timing MULTIBUS I mode
requires at least one wait state in the bus cycle since
the command outputs are delayed The non-
MULTIBUS I mode does not delay any outputs and
does not require wait states The MB input affects
the timing of the command and DEN outputs
and INTA) control outputs (ALE DEN DT R) and
control inputs (CEN AEN CENL CMDLY MB and
READY) are identical for all read bus cycles Read
cycles differ only in which command output is acti-
vated The MCE control output is only asserted dur-
ing interrupt acknowledge cycles
Write bus cycles activate different control and com-
mand outputs with different timing than read bus cy-
cles Memory write and I O write are write bus cy-
cles whose timing for command outputs (MWTC and
IOWC) control outputs (ALE DEN DT R) and con-
trol inputs (CEN AEN CENL CMDLY MB and
READY) are identical They differ only in which com-
mand output is activated
Halt bus cycles are different because no command
or control output is activated All control inputs are
ignored until the next bus cycle is started via S1 and
S0
Command and Control Outputs
The type of bus cycle performed by the local bus
master is encoded in the M IO S1 and S0 inputs
Different command and control outputs are activat-
ed depending on the type of bus cycle Table 2 indi-
cates the cycle decode done by the M82C288 and
the effect on command DT R ALE DEN and MCE
outputs
Bus cycles come in three forms read write and
halt Read bus cycles include memory read I O
read and interrupt acknowledge The timing of the
associated read command outputs (MRDC IORC
Static Operation
All M82C288 circuitry is of static design Internal reg-
isters and logic are static and require no refresh as
with dynamic circuit design This eliminates the mini-
mum operating frequency restriction placed on the
HMOS M82288 The CHMOS III M82C288 can oper-
ate from DC to the appropriate upper frequency limit
4
M82C288
The clock may be stopped in either state (HIGH
LOW) and held there indefinitely
Power dissipation is directly related to operating fre-
quency As the system frequency is reduced so is
the operating power When the clock is stopped to
the M82C288 power dissipation is at a minimum
This is useful for low-power and portable applica-
tions
Separate DEN and DT R outputs control the data
transceivers for all buses Bus contention is eliminat-
ed by disabling DEN before changing DT R The
DEN timing allows sufficient time for tristate bus driv-
ers to enter 3-state OFF before enabling other driv-
ers onto the same bus
The term CPU refers to any M80286 processor or
M80286 support component which may become an
M80286 local bus master and thereby drive the
M82C288 status inputs
FUNCTIONAL DESCRIPTION
Description
The M82C288 bus controller is used in M80286 sys-
tems to provide address latch control data trans-
ceiver control and standard level-type command
outputs The command outputs are timed and have
sufficient drive capabilities for large TTL buses and
meet all IEEE-796 requirements for MULTIBUS I A
special MULTIBUS I mode is provided to satisfy all
address data setup and hold time requirements
Command timing may be tailored to special needs
via a CMDLY input to determine the start of a com-
mand and READY to determine the end of a com-
mand
Connection to multiple buses are supported with a
latched enable input (CENL) An address decoder
can determine which if any bus controller should be
enabled for the bus cycle This input is latched to
allow an address decoder to take full advantage of
the pipelined timing on the M80286 local bus
Buses shared by several bus controllers are sup-
ported An AEN input prevents the bus controller
from driving the shared bus command and data
signals except when enabled by an external MULTI-
BUS I type bus arbiter
Processor Cycle Definition
Any CPU which drives the local bus uses an internal
clock which is one half the frequency of the system
clock (CLK) (see Figure 3) Knowledge of the phase
of the local bus master internal clock is required for
proper operation of the M80286 local bus The local
bus master informs the bus controller of its internal
clock phase when it asserts the status signals
Status signals are always asserted beginning in
Phase 1 of the local bus master’s internal clock
M82C284
(FOR REFERENCE)
271077 – 3
Figure 3 CLK Relationship to the Processor
Clock and Bus T-States
5
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