128Kx8 Monolithic SRAM
SMD 5962-89598
EDI88130CS
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
CS1#, CS2 & OE# Functions for Bus Control
Inputs and Outputs Directly TTL Compatible
Organized as 128Kx8
Commercial, Industrial and Military Temperature Ranges
Thru-hole and Surface Mount Packages JEDEC Pinout
• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)
• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)
• 32 lead Ceramic SOJ (Package 140)
• 32 pad Ceramic Quad LCC (Package 12)
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
Single +5V (±10%) Supply OperationThe EDI88130CS is
a high speed, high performance, 128Kx8 bits monolithic
Static RAM.
An additional chip enable line provides system memory security
during power down in non-battery backed up systems and memory
banking in high speed battery backed systems where large multiple
pages of memory are required.
The EDI88130CS has eight bi-directional input-output lines to provide
simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data retention
function for battery back-up applications.
Military product is available compliant to MIL-PRF-38535.
* 15ns access time is advanced information, contact factory for availability.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CS2#
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
32 QUAD LCC
TOP VIEW
A12
A14
A16
NC
V
CC
A15
CS2
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
V
CC
V
SS
NC
Data Input/Output
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Not Connected
4
3
2
1
32
31
30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
28
27
26
25
24
23
22
21
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
Block Diagram
Memory Array
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
A0-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS1#
CS2
OE#
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1
4248.15E-0816-ss-EDI88130CS
EDI88130CS
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Operating Temperature T
A
(Ambient)
Industrial
Military
Storage Temperature, Ceramic
Power Dissipation
Output Current
Junction Temperature, T
J
-0.2 to 7.0
-40 to +85
-55 to +125
-65 to +150
1.7
40
175
Unit
V
°C
°C
°C
W
mA
°C
OE# CS1# CS2 WE#
X
H
X
X
X
X
L
X
H
L
H
H
L
L
H
H
X
L
H
L
TRUTH TABLE
Mode
Standby
Standby
Output Deselect
Read
Write
Output
High Z
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Icc1
Icc1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
T
A
= +25°C
Max
Parameter
Address Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss,
f = 1.0MHz
V
OUT
= Vcc or Vss,
f = 1.0MHz
LCC
6
8
CSOJ,DIP,
Flatpack
Unit
pF
pF
12
14
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+0.5
+0.8
Unit
V
V
V
V
Data Lines
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
V
CC
= 5.0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
Icc1
Icc2
Icc3
V
OL
V
OH
Conditions
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE# = V
IH
, CS1# = V
IL
, I
I/O
= 0mA, CS2 = V
IH
CS1#
≥
V
IH
and/or CS2
≤
V
IL
,
V
IN
≥
V
IH
or
≤
V
IL,
f = 0
CS1#
≥
V
CC
-0.2V and/or CS2
≤
0.2V
V
IN
≥
V
CC
-0.2V or V
IN
≤
0.2V, f = 0
I
OL
= 8.0mA
I
OH
= -4.0mA
(15-17ns)
(20ns)
(25-55ns)
(17-55ns)
(15ns)
CS (17-55ns)
CS (15ns)
LPS
Min
—
—
—
—
—
—
—
—
—
—
—
2.4
Typ
—
—
Max
±5
±10
300
225
200
25
60
10
15
5
0.4
—
Units
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
3
—
—
—
—
AC Test Conditions
Figure 1
Vcc
Figure 2
480Ω
Vcc
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
480Ω
Q
255Ω
30pF
Q
255Ω
5pF
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2
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4248.15E-0816-ss-EDI88130CS
EDI88130CS
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
Symbol
JEDEC
Alt.
t
AVAV
t
RC
t
AVQV
t
AA
t
E1LQV
t
ACS
t
E2HQV
t
ACS
t
E1LQX
t
CLZ
t
E2HQX
t
CLZ
t
E1HQZ
t
CHZ
t
E2LQZ
t
CHZ
t
AVQX
t
OH
t
GLQV
t
OE
t
GLQX
t
OLZ
t
GHQZ
t
OHZ
t
E1LICCH
t
PU
t
E2HICCH
t
PU
t
PD
t
E1HICCL
t
E2LICCL
t
PD
15ns*
Min
15
Max
15
15
15
5
5
6
6
3
6
0
5
0
0
15
15
0
0
17
17
0
6
0
0
20
20
3
6
0
8
5
5
7
7
3
7
Min
17
17ns
Max
17
17
17
5
5
8
8
Min
20
20ns
Max
20
20
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
* 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
1. This parameter is guaranteed by design but not tested.
Symbol
JEDEC
Alt.
t
AVAV
t
RC
t
AVQV
t
AA
t
E1LQV
t
ACS
t
E2HQV
t
ACS
t
E1LQX
t
CLZ
t
E2HQX
t
CLZ
t
E1HQZ
t
CHZ
t
E2LQZ
t
CHZ
t
AVQX
t
OH
t
OE
t
GLQV
t
GLQX
t
OLZ
t
GHQZ
t
OHZ
t
E1LICCH
t
PU
t
E2HICCH
t
PU
t
E1HICCL
t
PD
t
E2LICCL
t
PD
25ns
Min
25
Max
25
25
25
5
5
10
10
0
10
0
10
0
0
25
25
0
0
0
0
5
5
Min
35
35ns
Max
35
35
35
5
5
15
15
0
15
0
15
0
0
35
35
Min
45
45ns
Max
45
45
45
5
5
20
20
0
20
0
20
0
0
45
45
Min
55
55ns
Max
55
55
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
25
20
55
55
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4248.15E-0816-ss-EDI88130CS
EDI88130CS
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Chip Enable to End of Write
Symbol
JEDEC
t
AVAV
t
E1LWH
t
E1LE1H
t
E2HWH
t
E2HE2L
t
AVWL
t
AVE1L
t
AVE2H
t
AVWH
t
WLWH
t
WLE1H
t
WLE2L
t
WHAX
t
E1HAX
t
E2LAX
t
WHDX
t
E1HDX
t
E2LDX
t
WLQZ
t
DVWH
t
DVE1H
t
DVE2L
t
WHQX
15ns*
Alt.
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
Min
15
12
12
12
12
0
0
0
12
12
12
12
0
0
0
0
0
0
0
7
7
7
3
Max
Min
17
13
13
13
13
0
0
0
13
13
13
13
0
0
0
0
0
0
0
8
8
8
3
17ns
Max
Min
20
15
15
15
15
0
0
0
15
15
15
15
0
0
0
0
0
0
0
10
10
10
3
20ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
7
8
8
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Chip Enable to End of Write
Symbol
JEDEC
t
AVAV
t
E1LWH
t
E1LE1H
t
E2HWH
t
E2HE2L
t
AVWL
t
AVE1L
t
AVE2H
t
AVWH
t
AVEH
t
WLWH
t
WLE1H
t
WLE2L
t
WHAX
t
E1HAX
t
E2LAX
t
WHDX
t
E1HDX
t
E2LDX
t
WLQZ
t
DVWH
t
DVE1H
t
DVE2L
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
25ns
Min
Max
25
20
16
16
16
0
0
0
20
20
20
20
20
0
0
0
0
0
0
0
10
15
15
15
3
35ns
Min
Max
35
25
20
20
20
0
0
0
25
25
30
30
30
0
0
0
0
0
0
0
13
20
20
20
3
45ns
Min
Max
45
35
25
25
25
0
0
0
35
35
30
30
30
5
5
5
0
0
0
0
15
20
20
20
3
55ns
Min
Max
55
45
40
40
40
0
0
0
45
45
35
35
35
5
5
5
0
0
0
0
20
25
25
25
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
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4248.15E-0816-ss-EDI88130CS
EDI88130CS
FIGURE 2 – TIMING WAVEFORM – READ CYCLES
t
AVAV
ADDRESS
t
AVQV
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
CS1#
t
E1LQV
t
E1LQX
t
E1LICCH
Icc
t
E1HQZ
t
E1HICCL
t
E2LICCL
t
AVQV
DATA I/O
t
AVQX
CS2
DATA 1
DATA 2
t
E2HQV
t
E2HICCH
t
E2HQX
OE#
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
DATA I/O
t
GLQV
t
GLQX
t
GHQZ
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
FIGURE 3 – WRITE CYCLE 1
t
AVAV
ADDRESS
t
AVWL
WE#
t
AVWH
t
WLWH
t
WHAX
t
E1LWH
CS1#
CS2
t
E2HWH
t
DVWH
t
WHDX
DATA IN
t
WLQZ
DATA OUT
t
WHQX
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 –
WRITE CYCLES 2
t
AVAV
ADDRESS
ADDRESS
WRITE CYCLES 3
t
AVAV
t
AVE2H
t
AVE1L
WE#
t
E1LE1H
t
E1HAX
WE#
t
E2HE2L
t
E2LAX
CS1#
CS1#
CS2
CS2
t
DVE1H
DATA I/O
t
E1HDX
DATA I/O
t
DVE2L
t
E2LDX
WRITE CYCLE 2 – EARLY WRITE, CS1# CONTROLLED
WRITE CYCLE 3 – EARLY WRITE, CS2 CONTROLLED
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5
4248.15E-0816-ss-EDI88130CS
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