Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
80C550/83C550/87C550
DESCRIPTION
The Philips 8XC550 is a high-performance microcontroller fabricated
with Philips high-density CMOS technology. This Philips CMOS
technology combines the high speed and density characteristics of
HMOS with the low power attributes of CMOS. Philips epitaxial
substrate minimizes latch-up sensitivity. The CMOS 8XC550 has the
same instruction set as the 80C51.
The 8XC550 contains a 4k
×
8 EPROM (87C550)/ROM
(83C550)/ROMless (80C550 has no program memory on-chip), a
128
×
8 RAM, 8 channels of 8-bit A/D, four 8-bit ports (port 1 is input
only), a watchdog timer, two 16-bit counter/timers, a seven-source,
two-priority level nested interrupt structure, a serial I/O port for either
multi-processor communications, I/O expansion or full duplex UART,
and an on-chip oscillator and clock circuits.
In addition, the 8XC550 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
FEATURES
•
80C51 based architecture
– 4k
×
8 EPROM (87C550)/ROM (83C550)
– 128
×
8 RAM
– Eight channels of 8-bit A/D
– Two 16-bit counter/timers
– Watchdog timer
– Full duplex serial channel
– Boolean processor
•
Memory addressing capability
– 64k ROM and 64k RAM
•
Power control modes:
– Idle mode
– Power-down mode
•
CMOS and TTL compatible
•
One speed range at V
CC
= 5V
±10%
– 3.5 to 16MHz
•
Extended temperature ranges
•
OTP package available
ORDERING INFORMATION
ROMless
P80C550EBP N
P80C550EBA A
P80C550EFA A
ROM
P83C550EBP N
P83C550EBA A
P83C550EFA A
EPROM
P87C550EBP N
P87C550EBA A
P87C550EFA A
OTP
OTP
OTP
TEMPERATURE RANGE
°C
AND PACKAGE
1
0 to +70, Plastic Dual In-Line Package
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
FREQ
MHz
3.5 to 16
3.5 to 16
3.5 to 16
DRAWING
NUMBER
SOT129-1
SOT187-2
SOT187-2
NOTES:
1. OTP = One Time Programmable EPROM.
1998 May 01
2
853-1568 19329
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
80C550/83C550/87C550
PIN DESCRIPTION
PIN NO.
MNEMONIC
V
SS
V
CC
AV
CC
AV
SS
Vref+
Vref–
P0.0–0.7
39–32
DIP
20
40
1
2
LCC
24
44
1
4
2
3
43–36
TYPE
I
I
I
I
I
I
I/O
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Analog Power Supply:
Analog supply voltage.
Analog Ground:
Analog 0V reference.
Vref:
A/D converter reference level inputs. Note that these references are combined with AV
CC
and
AV
SS
in the 40-pin DIP package.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in
the S87C550. External pull-ups are required during program verification.
Port 1:
Port 1 is an 8-bit input only port (6-bit in the DIP package; bits P1.6 and P1.7 are not
implemented). Port 1 digital input can be read out any time.
ADCx:
Inputs to the analog multiplexer input of the 8-bit A/D. There are only six A/D inputs in the
DIP package.
I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 3 also serves the special features of the SC80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V
SS
permits a power-on reset using only an external capacitor to
V
CC
.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EPROM programming.
Program Store Enable:
The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low to enable
the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held
high, the device executes from internal program memory unless the program counter contains an
address greater than 0FFFH. For the 80C550 ROMless part, EA must be held low for the part to
operate properly. This pin also receives the 12.75V programming supply voltage (V
PP
) during
EPROM programming.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
NAME AND FUNCTION
P1.0–P1.7
ADC0–ADC7
P2.0–P2.7
3–8
3–8
21–28
5–12
5–12
25–32
I
P3.0–P3.7
10–17
14–21
I/O
10
11
12
13
14
15
16
17
RST
9
14
15
16
17
18
19
20
21
13
I
O
I
I
I
I
O
O
I
ALE/PROG
30
34
I/O
PSEN
29
33
O
EA/V
PP
31
35
I
XTAL1
XTAL2
19
18
23
22
I
O
1998 May 01
5
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